IP Library Granted Patent US 7,759,926
Granted Patent B2
US 7,759,926 · App. 11/362,289 · Granted Jul 20, 2010

Dynamic phase offset measurement

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Quick Facts
Patent No.
US 7,759,926
App. No.
11/362,289
Granted
Jul 20, 2010
Kind
B2
Abstract

In one embodiment, a method is provided for measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode. The method includes: in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement; in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and comparing the spread spectrum phase jitter measurement to the static phase jitter measurement to determine the dynamic phase offset.

Claims (13)

1. A method of measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode, comprising:

in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement;

in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and

calculating a difference between the spread spectrum phase jitter measurement and the static phase jitter measurement to provide the measurement of the dynamic phase offset.

2. The method of claim 1 , wherein the spread spectrum phase jitter measurement is measured over a number of input clock cycles and the static phase jitter measurement is measured over the same number of input clock cycles.

3. The method of claim 2 , further comprising:

determining the number of input clock cycles by selecting the maximum of a predefined number and a number of cycles of the input clock within a period of the spread spectrum modulation.

4. The method of claim 2 , wherein the number of input clock cycles is at least 2000.

5. The method of claim 1 , wherein the spread spectrum phase jitter measurement includes a plurality of spread spectrum phase jitter measurements and the static phase jitter measurement includes a plurality of static phase jitter measurements.

6. The method of claim 5 , wherein a range for the plurality of spread spectrum phase jitter measurements extends from a most positive spread spectrum phase jitter measurement to a most negative spread spectrum phase jitter measurement.

7. The method of claim 5 , wherein a range for the plurality of static phase jitter measurements extends from a most positive static phase jitter measurement to a most negative static phase jitter measurement.

8. The method of claim 1 , wherein measuring the phase jitter in the spread spectrum and static modes comprises measuring the phase jitter with an oscilloscope.

9. The method of claim 1 , wherein measuring the phase jitter in the spread spectrum and static modes comprises measuring the phase jitter with a time interval analyzer.

Assignments (4)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
SECURITY INTEREST Recorded Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035223/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2006
From: NIKOLOV, LUDMIL; FRANCE, MICHAEL G.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017277/0148 →