Area efficient routing architectures for programmable logic devices

1. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

an interconnect adapted to provide global routing resources within the programmable logic device;

a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and

a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises:

a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices, wherein the subset of the signals is less than a number of input ports for lookup tables within the logic block slice; and

a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit.

2. The programmable logic device of claim 1 , wherein the first input routing circuit comprises a two-stage input switch box and the first routing circuit comprises a switch box having a plurality of multiplexers.

3. The programmable logic device of claim 1 , wherein the second input switch stage comprises a full cross bar stage.

4. The programmable logic device of claim 1 , further comprising:

an output routing circuit, corresponding to each programmable logic block, adapted to receive output signals from the logic block slices within the corresponding programmable logic block and route the output signals directly to the first routing circuit and the first input routing circuit.

5. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

an interconnect adapted to provide global routing resources within the programmable logic device;

a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and

a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises:

a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices; and

a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit,

wherein each of the logic block slices comprises at least a first and a second slice each having at least a first lookup table, with the programmable logic blocks each comprising at least a first logic block slice, a second logic block slice, and a third logic block slice; and

wherein the first logic block slice is a logic block slice type different from the second logic block slice, and the third logic block slice is a logic block slice type different from the first and second logic block slices.

6. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

an interconnect adapted to provide global routing resources within the programmable logic device;

a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and

a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises:

a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices; and

a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit,

wherein the programmable logic blocks are homogeneous within the programmable logic device.

7. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

an interconnect adapted to provide global routing resources within the programmable logic device;

a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and

a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises:

a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices; and

a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit,

wherein the programmable logic blocks are heterogeneous within the programmable logic device.

8. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

an interconnect adapted to provide global routing resources within the programmable logic device;

a first routing circuit, corresponding to each programmable logic block, adapted to provide global signal routing connectivity within the programmable logic device via the interconnect for the corresponding programmable logic block; and

a first input routing circuit, corresponding to each programmable logic block, adapted to receive signals from the first routing circuit and route to the plurality of logic block slices within the corresponding programmable logic block, wherein the first input routing circuit comprises:

a first input switch stage adapted to receive signals from the first routing circuit and provide a subset of the signals for each of the logic block slices; and

a second input switch stage, corresponding to each logic block slice, adapted to receive the corresponding subset of the signals from the first input switch stage and selectively route to the corresponding logic block slice, wherein the second input switch stage is further adapted to receive a first plurality of signals directly from the first routing circuit,

wherein the logic block slices each comprise a dual-slice architecture, and wherein a first logic block slice comprises a plurality of lookup tables but no registers or RAM functionality, a second logic block slice comprises a plurality of registers and a plurality of lookup tables but no RAM functionality, and a third logic block slice comprises a plurality of registers and a plurality of lookup tables adapted to provide RAM functionality.

9. The programmable logic device of claim 1 , further comprising:

a volatile memory block adapted to store information during operation of the programmable logic device;

configuration memory adapted to configure the programmable logic device;

a non-volatile memory block adapted to store configuration data for transfer to the configuration memory to configure the programmable logic blocks;

input/output blocks adapted to transfer information into and out of the programmable logic device; and

wherein the interconnect is configured based on the configuration data stored in the configuration memory and is adapted to provide routing resources between the volatile memory block, the input/output blocks, and the programmable logic blocks.

10. A programmable logic device comprising:

a plurality of programmable logic blocks;

a plurality of logic block slices within each of the programmable logic blocks;

means for globally routing signals within the programmable logic device for the programmable logic blocks;

means, corresponding to each programmable logic block, for providing global signal routing connectivity to the global routing means; and

means, corresponding to each programmable logic block, for routing in a first and a second stage signals from the providing means to the plurality of logic block slices within the corresponding programmable logic block, wherein the routing means is further adapted to route the signals directly to the second stage by bypassing the first stage,

wherein the programmable logic blocks are heterogeneous within the programmable logic device.

11. The programmable logic device of claim 10 , wherein the signals provided from the first stage to the second stage of the routing means for each of the plurality of logic block slices is less than a number of input ports for lookup tables within each of the logic block slices.

12. The programmable logic device of claim 10 , further comprising means, corresponding to each programmable logic block, for routing output signals from the logic block slices within the corresponding programmable logic block directly to the providing means and the routing means.

13. The programmable logic device of claim 10 , wherein each of the logic block slices comprises at least a first and a second slice each having at least a first lookup table, with the programmable logic blocks each comprising at least a first logic block slice, a second logic block slice, and a third logic block slice;

wherein the first logic block slice is a logic block slice type different from the second logic block slice, and the third logic block slice is a logic block slice type different from the first and second logic block slices; and

wherein the first logic block slice comprises a plurality of lookup tables but no registers or RAM functionality, the second logic block slice comprises a plurality of registers and a plurality of lookup tables but no RAM functionality, and the third logic block slice comprises a plurality of registers and a plurality of lookup tables adapted to provide RAM functionality.

14. The programmable logic device of claim 10 , further comprising:

a volatile memory block adapted to store information during operation of the programmable logic device;

configuration memory adapted to configure the programmable logic device;

a non-volatile memory block adapted to store configuration data for transfer to the configuration memory to configure the programmable logic blocks;

input/output blocks adapted to transfer information into and out of the programmable logic device; and

wherein the global routing means is configured based on the configuration data stored in the configuration memory and is adapted to provide routing resources between the volatile memory block, the input/output blocks, and the programmable logic blocks.

15. A method for providing a routing architecture within a programmable logic device, the method comprising:

providing a plurality of programmable logic blocks;

providing at least a first logic block slice, a second logic block slice, and a third logic block slice within each of the programmable logic blocks, with the first, second, and third logic block slices each of a different logic block slice type, and wherein the first logic block slice comprises a plurality of lookup tables but no registers or RAM functionality, the second logic block slice comprises a plurality of registers and a plurality of lookup tables but no RAM functionality, and the third logic block slice comprises a plurality of registers and a plurality of lookup tables adapted to provide RAM functionality;

providing an interconnect to provide global routing resources within the programmable logic device;

providing a first routing circuit for each programmable logic block to provide signal routing connectivity within the programmable logic device locally for the programmable logic block and to other ones of the programmable logic blocks via the interconnect;

providing a two-stage routing circuit for each programmable logic block for routing signals from the first routing circuit to the logic block slices within the corresponding programmable logic block; and

providing an output routing circuit for routing output signals from the logic block slices within the corresponding programmable logic block directly to the first routing circuit and the two-stage routing circuit.

16. The method of claim 15 , further comprising receiving, by a second stage of the two-stage routing circuit, a first plurality of signals directly from the first routing circuit.

17. The programmable logic device of claim 5 , wherein the first input routing circuit comprises a two-stage input switch box and the first routing circuit comprises a switch box having a plurality of multiplexers.

18. The programmable logic device of claim 6 , wherein the first input routing circuit comprises a two-stage input switch box and the first routing circuit comprises a switch box having a plurality of multiplexers.

19. The programmable logic device of claim 7 , wherein the first input routing circuit comprises a two-stage input switch box and the first routing circuit comprises a switch box having a plurality of multiplexers.

20. The programmable logic device of claim 8 , wherein the first input routing circuit comprises a two-stage input switch box and the first routing circuit comprises a switch box having a plurality of multiplexers.