Design features for testing integrated circuits
View Patent ↗Systems and methods are disclosed herein to provide test features for integrated circuits. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an input signal path adapted to route an address signal for a configurable memory. An input multiplexer, coupled to the input signal path, is controllable to route a first test signal provided via the input signal path for at least one memory configuration that does not use the input signal path for the address signal.
1. An integrated circuit comprising:
a wordline driver having an address input terminal, an enable input terminal, and a driver output terminal, the wordline driver configured to drive wordlines in a memory;
an address decoder coupled to the address input terminal of the wordline driver;
a multiplexer having an output terminal, input terminals, and a select terminal, the output terminal of the multiplexer coupled to the enable input terminal of the wordline driver;
an enable signal source coupled to a first input terminal of the multiplexer for asserting a wordline enable signal, the wordline enable signal possibly causing a failure of the integrated circuit if asserted before new address signals from the address decoder to the wordline driver have settled;
a test signal source coupled to a second input terminal of the multiplexer for asserting a wordline enable test signal, the timing of the wordline enable test signal controllable to test whether a failure of the integrated circuit is due to the wordline enable signal being asserted before new address signals from the address decoder to the wordline driver have settled; and
a control signal source coupled to the select terminal of the multiplexer,
wherein the multiplexer is responsive to the control signal source in coupling either the enable signal source or the test signal source to the enable input terminal of the wordline driver.
2. The integrated circuit of claim 1 , wherein the enable signal source comprises:
logic circuitry adapted to receive and combine a chip enable signal and a chip select signal and to generate at its output a wordline enable signal based on the combination; and
a delay element coupled to the output of the logic circuitry and to the first input terminal of the multiplexer.
3. The integrated circuit of claim 1 , wherein the test signal source comprises a configuration fuse adapted to be configured with a test signal.
4. The integrated circuit of claim 1 , wherein the test signal source comprises an unused input pin adapted to receive a test signal.
5. The integrated circuit of claim 1 , wherein the control signal source comprises a configuration fuse adapted to be configured with a control signal.