Circuit layout for improved performance while preserving or improving density
View Patent ↗In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.
1. A programmable logic cell comprising:
a grounded bent-gate transistor electrically isolating a cell input from a cell output stage.
2. The programmable logic cell of claim 1 , further comprising:
the grounded bent-gate transistor forming an at least partially widened active region with a transistor of the cell output stage where the cell output stage receives an input from a cell input stage.
3. The programmable logic cell of claim 1 , further comprising:
the grounded bent-gate transistor forming an at least partially widened active region with a transistor of a cell input stage where the cell input stage receives the cell input.
4. The programmable logic cell of claim 1 , further comprising:
a first multiplexer and a second multiplexer, an input stage of the first multiplexer coupled to an input stage of the second multiplexer.
5. The programmable logic cell of claim 4 , further comprising:
the first multiplexer and the second multiplexer each having bent-gate transistors joined to form an at least partially widened active region between the bent-gate transistors.
6. The programmable logic cell of claim 4 , further comprising:
a third multiplexer and a fourth multiplexer sharing gate drives with input stages of the first and second multiplexers.
7. The programmable logic cell of claim 6 , further comprising:
the third multiplexer and the fourth multiplexer each having bent-gate transistors joined to form an at least partially widened active region between the bent-gate transistors.
8. A circuit comprising:
at least one bent-gate grounded-gate transistor electrically isolating an output stage from a circuit input.
9. The circuit of claim 8 , wherein the circuit is a multiplexer.
10. The circuit of claim 8 , further comprising:
the at least one grounded-gate transistors coupled to at least partially widen an active region where a circuit input stage receives the circuit input, and to at least partially widen an active region where the output stage receives an input from the input stage.
11. The circuit of claim 10 , further comprising:
the output stage comprising a bent-gate transistor where the output stage receives the input from the input stage.
12. The circuit of claim 8 , further comprising:
at least one bent-gate grounded-gate transistor electrically isolating a second output stage from a second circuit input.
13. The circuit of claim 8 , further comprising:
two input stages each comprising a pair of bent-gate transistors.
14. The circuit of claim 10 , wherein the at least one grounded-gate transistors coupled to at least partially widen an active region where the output stage receives the input from the input stage further comprises:
the at least one grounded-gate transistor coupled to create an at least partially widened active region at a point where the output stage is coupled to an active region shared by two or more transistors of the circuit input stage.