Selective loading of configuration data into configuration memory cells

1. A programmable logic device comprising:

a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data;

a plurality of configuration memory cells; and

control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells, wherein the first bit is adapted to be programmed in response to a loading of the configuration data into the non-volatile memory.

2. The programmable logic device of claim 1 , wherein the second bit is adapted to be programmed to prevent a loading of the configuration data from the non-volatile memory into the configuration memory cells.

3. The programmable logic device of claim 1 , wherein the first bit is adjacent to the second bit in the non-volatile memory.

4. The programmable logic device of claim 1 , further comprising a data port adapted to receive instructions to program the first and second bits.

5. The programmable logic device of claim 1 , wherein the control logic comprises a register adapted to receive the first bit and the second bit from the non-volatile memory.

6. The programmable logic device of claim 1 , further comprising a plurality of sense amplifiers adapted to provide the first bit and the second bit to the control logic.

7. The programmable logic device of claim 1 , wherein the configuration memory cells are volatile SRAM memory cells.

8. The programmable logic device of claim 1 , wherein the non-volatile memory is a flash memory.

9. A method of controlling a programmable logic device, the method comprising:

pre-programming a first bit and a second bit of a non-volatile memory with a first logic state, wherein the non-volatile memory is adapted to store the first bit, the second bit, and a plurality of configuration data;

erasing the non-volatile memory, wherein the first bit and the second bit each exhibit a second logic state following the erasing;

loading the configuration data into the non-volatile memory;

programming the first bit with the first logic state to identify that the loading is completed; and

selectively programming a second bit with the first logic state to identify whether a user desires that the configuration data be loaded into a plurality of configuration memory cells.

10. The method of claim 9 , further comprising:

performing a logic operation on the first bit and the second bit to obtain a logic result; and

selectively loading the configuration data from the non-volatile memory into a plurality of configuration memory cells in response to the logic result.

11. The method of claim 9 , wherein the method is performed in response to instructions received by the programmable logic device.

12. The method of claim 9 , wherein the configuration memory cells are volatile SRAM memory cells.

13. The method of claim 9 , wherein the non-volatile memory is a flash memory.

14. The method of claim 9 , further comprising:

reading the first bit and the second bit; and

selectively loading the configuration data from the non-volatile memory into the plurality of configuration memory cells based on logic states of the first and second bits.

15. The method of claim 14 , wherein the selectively loading comprises performing a logic operation on the first bit and the second bit to obtain a logic result.

16. The method of claim 14 , wherein the reading and selectively loading are performed by control logic of the programmable logic device.

17. The method of claim 14 , wherein the reading and selectively loading are performed in response to a powering up of the programmable logic device.

18. The method of claim 14 , wherein the reading comprises loading the first bit and the second bit into a register.

19. The method of claim 14 , wherein the configuration memory cells are volatile memory cells.

20. The method of claim 14 , wherein the first bit is a validation bit and the second bit is a stop bit.

21. The method of claim 14 , wherein the configuration data is loaded from the non-volatile memory into the plurality of configuration memory cells based on the first and second bits having opposite logic states.

22. The method of claim 21 , wherein the first bit has a logical high state and the second bit has a logical low state.

23. A programmable logic device comprising:

a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data;

a plurality of configuration memory cells; and

control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells, wherein the second bit is adapted to be programmed to prevent a loading of the configuration data from the non-volatile memory into the configuration memory cells.