Soft error detection logic testing systems and methods

1. A programmable logic device comprising:

configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the configuration memory cell and a second port for writing RAM data to the configuration memory cell;

soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory cell adapted to function as RAM by calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory; and

a fuse configurable in a first logic state to enable the SED logic to read RAM data stored in the configuration memory cell through the first port and configurable in a second logic state to prevent the SED logic from reading the RAM data stored in the configuration memory cell,

wherein the SED logic can be tested for correct operation by configuring the fuse to enable the SED logic to include the RAM data in calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory that does not include the RAM data.

2. The programmable logic device of claim 1 including:

an address shift register adapted to provide wordline signals on wordlines to the configuration memory including the configuration memory cell adapted to function as RAM; and

a multiplexer coupled between the address shift register and a wordline to the configuration memory cell, the multiplexer having a first input coupled to the address shift register, a second input coupled to a second signal source, an output coupled to the wordline, and a select input coupled to the fuse,

wherein the multiplexer couples the address shift register to the wordline with the fuse configured in the first logic state to enable reading of the RAM data through the first port, and couples the second signal source to the wordline with the fuse configured in the second logic state to disable reading of the RAM data through the first port.

3. The programmable logic device of claim 1 , wherein the SED logic is implemented within configuration logic of the programmable logic device.

4. The programmable logic device of claim 1 , wherein the SED logic is adapted to calculate a present cyclic redundancy code (CRC) value for comparison with a pre-calculated CRC value.

5. The programmable logic device of claim 1 , wherein the fuse is a configuration memory cell.

6. A programmable logic device comprising:

configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the memory cell having a first port for writing configuration data to the configuration memory cell and a second port for writing RAM data to the configuration memory cell;

soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory cell adapted to function as RAM by calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory; and

testing means configurable in a first state for enabling the SED logic to read RAM data stored in the configuration memory cell through the first port and configurable in a second state to prevent the SED logic from reading the RAM data stored in the configuration memory cell,

wherein the SED logic can be tested for correct operation by configuring the testing means to enable the SED logic to include the RAM data in calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory that does not include the RAM data.

7. A method of testing soft error detection (SED) logic for correct operation within a programmable logic device having configuration memory that includes a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the configuration memory cell and a second port for writing RAM data to the configuration memory cell, the method comprising:

selecting a configuration memory cell for testing purposes;

writing RAM data representing a soft error to the selected configuration memory cell through the second port; and

with the SED logic:

reading the RAM data stored in the selected configuration memory cell through the first port;

calculating a present data value for the configuration memory that includes the RAM data read from the selected configuration memory cell; and

comparing the present data value with a pre-calculated data value for the configuration memory that does not include the RAM data,

wherein the SED logic is operating correctly if the present data value does not match the pre-calculated data value.

8. The method of claim 7 including prior to the SED logic reading the RAM data stored in the configuration memory cell through the first port:

configuring the programmable logic device to enable the SED logic to read the RAM data through the first port of the selected configuration memory cell,

wherein the SED logic is prevented from reading the RAM data during normal operation of the SED logic.

9. The method of claim 7 , wherein the present data value and pre-calculated data value are cyclic redundancy code (CRC) values.

10. The programmable logic device of claim 1 , wherein the RAM is distributed RAM.

11. The programmable logic device of claim 6 , wherein the RAM is distributed RAM.

12. The method of claim 7 , wherein the RAM is distributed RAM.

13. The programmable logic device of claim 1 including:

a second fuse configurable in a first logic state to enable the RAM data to be written to the configuration memory cell through the second port and configurable in a second logic state to prevent the RAM data from being written to the configuration memory cell.