Digital I/O timing control
View Patent ↗When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.
1. Apparatus for applying a desired phase shift to an input clock signal to generate a delayed clock signal, the apparatus comprising:
a delay count generator adapted to generate a delay count value corresponding to the desired phase shift; and
a slave delay module adapted to delay the input clock signal based on the delay count value to generate the delayed clock signal, wherein the delay count generator comprises:
a counter adapted to count cycles of a high-frequency clock signal having a frequency greater than that of the input clock signal; and
control logic adapted to control the counting operation of the counter based on the input clock signal to generate the delay count value.
2. The apparatus of claim 1 , wherein the delay count generator further comprises circuitry adapted to generate the high-frequency clock signal.
3. The apparatus of claim 2 , wherein the circuitry is a ring oscillator.
4. The apparatus of claim 1 , wherein:
the delay count generator further comprises a clock divider adapted to generate a divided-down version of the input clock signal; and
the control logic is adapted to control the counting operation of the counter based on the divided-down clock signal to generate the delay count value.
5. The apparatus of claim 4 , wherein the control logic is adapted to apply the divided-down clock signal as an enable signal for the counter, such that the counter is enabled for a half cycle of the divided-down clock signal.
6. The apparatus of claim 1 , wherein the slave delay module comprises a string of delay elements and is adapted to select an output of a delay element in the string corresponding to the delay count value.
7. The apparatus of claim 6 , wherein each delay element in the slave delay module applies an amount of delay equivalent to the period of the high-frequency clock signal.
8. The apparatus of claim 1 , wherein the delay count generator further comprises:
a first register adapted to store a value based on a counter value generated by the counter; and
a second register adapted to store the value stored in the first register, wherein:
the value is loaded into the first register based on a first load control signal generated by the control logic; and
the value is loaded into the second register based on an externally generated second load control signal.
9. The apparatus of claim 1 , wherein the apparatus is implemented in a single integrated circuit.
10. The apparatus of claim 9 , wherein the single integrated circuit is an FPGA.
11. The apparatus of claim 1 , wherein:
the delay count generator further comprises:
circuitry adapted to generate the high-frequency clock signal;
a clock divider adapted to generate a divided-down version of the input clock signal;
a first register adapted to store a value based on a counter value generated by the counter; and
a second register adapted to store the value stored in the first register, wherein:
the value is loaded into the first register based on a first load control signal generated by the control logic; and
the value is loaded into the second register based on an externally generated second load control signal;
the control logic is adapted to control the counting operation of the counter based on the divided-down clock signal to generate the delay count value;
the slave delay module comprises a string of delay elements and is adapted to select an output of a delay element in the string corresponding to the delay count value; and
the apparatus is implemented in a single integrated circuit.
12. The apparatus of claim 11 , wherein:
the circuitry is a ring oscillator;
the control logic is adapted to apply the divided-down clock signal as an enable signal for the counter, such that the counter is enabled for a half cycle of the divided-down clock signal;
each delay element in the slave delay module applies an amount of delay equivalent to the period of the high-frequency clock signal; and
the single integrated circuit is an FPGA.
13. A method for applying a desired phase shift to an input clock signal to generate a delayed clock signal, the method comprising:
generating a delay count value corresponding to the desired phase shift; and
delaying the input clock signal based on the delay count value to generate the delayed clock signal, wherein the delay count value is generated by:
counting cycles of a high-frequency clock signal having a frequency greater than that of the input clock signal; and
controlling the counting operation based on the input clock signal to generate the delay count value.
14. The method of claim 13 , further comprising generating the high-frequency clock signal.
15. The method of claim 13 , further comprising generating a divided-down version of the input clock signal, wherein the counting operation is controlled based on the divided-down clock signal to generate the delay count value.
16. The method of claim 13 , further comprising:
storing in a first register a value based on a counter value generated by the counting operation; and
storing in a second register the value stored in the first register, wherein:
the value is loaded into the first register based on a locally generated first load control signal; and
the value is loaded into the second register based on an externally generated second load control signal.
17. The method of claim 13 , wherein the method is implemented in an FPGA.
18. The method of claim 13 , further comprising:
generating the high-frequency clock signal;
generating a divided-down version of the input clock signal, wherein the counting operation is controlled based on the divided-down clock signal to generate the delay count value;
storing in a first register a value based on a counter value generated by the counting operation; and
storing in a second register the value stored in the first register, wherein:
the value is loaded into the first register based on a locally generated first load control signal; and
the value is loaded into the second register based on an externally generated second load control signal, wherein the method is implemented in a single integrated circuit.
19. The method of claim 18 , wherein the single integrated circuit is an FPGA.
20. An apparatus for applying a desired phase shift to an input clock signal to generate a delayed clock signal, the apparatus comprising:
means for generating a delay count value corresponding to the desired phase shift; and
means for delaying the input clock signal based on the delay count value to generate the delayed clock signal, wherein the delay count value is generated by:
means for counting cycles of a high-frequency clock signal having a frequency greater than that of the input clock signal; and
means for controlling the counting operation based on the input clock signal to generate the delay count value.