Efficient configuration of daisy-chained programmable logic devices
In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.
1. A programmable logic device, comprising:
a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories;
a serial interface processor adapted to command the bitstream selection by the multiplexer;
a latch adapted to store at least a portion of a leading read address signal provided by the serial interface processor to the plurality of serial interface memories; and
a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.
2. The programmable logic device of claim 1 , wherein the programmable logic device is a master field programmable logic device (FPGA) adapted to provide the decompressed configuration bitstream to at least one daisy-chained slave FPGA.
3. The programmable logic device of claim 1 , wherein the plurality of serial interface memories are serial peripheral interface (SPI) flash memories and the serial interface processor is an SPI processor.
4. The programmable logic device of claim 3 , further comprising:
an interface for receiving a size command indicating the number of SPI flash memories within the plurality, and wherein the SPI processor is further adapted to gate a read clock responsive to the size command.
5. The programmable logic device of claim 1 further comprising:
a memory interface adapted to receive a first address signal from an external source and couple the first address signal to the latch such that the latch may store the first address signal as the at least a portion of the leading read address signal.
6. The programmable logic device of claim 5 , further comprising:
a configuration memory, wherein the latch is further adapted to store a second address signal stored by the configuration memory as the at least a portion of the leading read address signal.
7. A programmable logic device, comprising:
a memory interface adapted to receive a first address signal from an external source;
configuration memory cells adapted to store a second address signal;
an SPI processor adapted to select either the first address signal or the second address signal and to provide the selected address as a leading read address to a plurality of SPI flash memories; and
a multiplexer adapted to select from a serial output signal from each of the SPI flash memories to provide a configuration bitstream input signal, the SPI processor being further adapted to command the selection by the multiplexer.
8. The programmable logic device of claim 7 , wherein the SPI processor is further adapted to command the gating of a read clock to provide an SPI read clock to the plurality of SPI flash memories.
9. The programmable logic device of claim 8 , wherein the SPI processor is further adapted to provide a read command to the plurality of SPI flash memories using a high-during-configuration (HDC) signal.
10. The programmable logic device of claim 7 , further comprising:
a latch adapted to store at least a portion of the leading read address signal provided by the SPI processor.
11. A system comprising:
a plurality of serial interface memory devices, each adapted to store a configuration bitstream;
a master field programmable gate array (FPGA) coupled to the plurality of serial interface memories to receive their bitstreams, the master PLD including:
a multiplexer adapted to select the configuration bitstream from each of the plurality serial interface memories; and
a serial interface processor adapted to command the bitstream selection by the multiplexer; and
one or more slave FPGAs daisy chained to the master FPGA and adapted to receive a configuration bitstream from the master FPGA.
12. The system of claim 11 , wherein the master FPGA further includes a bitstream decompressor adapted to decompress the configuration bitstream received from the serial interface memories, the master FPGA adapted to provide a decompressed configuration bitstream to the one or more slave FPGAs.
13. The system of claim 11 , wherein the serial interface memories are serial peripheral interface (SPI) memories.
14. The system of claim 11 , wherein the master FPGA further includes:
a latch adapted to store at least a portion of a leading read address signal provided by the serial interface processor to the plurality of serial interface memories.
15. The system of claim 14 , wherein the master FPGA further includes:
a memory interface adapted to receive a first address signal from an external source and couple the first address signal to the latch such that the latch may store the first address signal as the at least a portion of the leading read address signal.
16. The system of claim 15 , wherein the master FPGA further includes:
a configuration memory, wherein the latch is further adapted to store a second address signal stored by the configuration memory as the at least a portion of the leading read address signal.
17. The system of claim 15 , wherein the master FPGA further includes:
an interface for receiving a size command indicating the number of serial interface memories.
18. The system of claim 17 , wherein the serial interface memories are SPI flash memories and wherein the serial interface processor is an SPI interface processor.