IP Library Granted Patent US 9,294,051
Granted Patent B2
US 9,294,051 · App. 14/209,785 · Granted Mar 22, 2016

Method and apparatus for implementing wide data range and wide common-mode receivers

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Quick Facts
Patent No.
US 9,294,051
App. No.
14/209,785
Granted
Mar 22, 2016
Kind
B2
Abstract

Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.

Claims (23)

1. A sense amplifier comprising:

a power switch coupled between a first reference voltage source at a first voltage level and a second reference voltage source at a second voltage level lower than the first voltage level, the power switch configured to enable current to flow from the first reference voltage source to the second reference voltage source in the sense amplifier responsive to a clock signal placed in a first state;

a sensing circuit coupled in series with the power switch, the sensing circuit configured to receive an input signal and change an output voltage at an output node based on the input signal during a period between a first time at which the clock signal transitions from a second state to the first state and a second time at which the output voltage reaches a threshold voltage level;

a regeneration circuit coupled in parallel to the sensing circuit and in series with the power switch, the regeneration circuit configured to amplify the changed output voltage after the second time and before the clock signal transitions from the first state to the second state, the output voltage reaching the threshold voltage level based on the current flowing from the first reference voltage source to the second reference voltage source through the power switch; and

a self clock control circuit configured to turn off the power switch responsive to the output voltage at the output node reaching a holding voltage level, the output node coupled to an input of the self clock control circuit and an output of the self clock control circuit coupled to a control terminal of the power switch.

2. The sense amplifier of claim 1 , further comprising:

a reset circuit coupled to the output node and configured to set the output voltage at the output node to a predetermined voltage level responsive to the clock signal placed in the second state.

3. The sense amplifier of claim 1 , wherein the regeneration circuit is configured to amplify the changed output voltage after the second time without receiving another clock signal.

4. The sense amplifier of claim 1 , wherein the sensing circuit comprises a transistor coupled to the output node in series with the power switch and configured to increase or decrease the output voltage based on the input signal.

5. The sense amplifier of claim 1 , further comprising a sensing current control circuit coupled in series with the sensing circuit and configured to control a degree of change in the output voltage caused by operation of the sensing circuit.

6. The sense amplifier of claim 1 , wherein the regeneration circuit comprises cross coupled transistors, and the output node is coupled to a regeneration port of the cross coupled transistors.

7. The sense amplifier of claim 6 , wherein the regeneration circuit further comprises a regeneration current control circuit coupled in series with the power switch and the regeneration circuit, and configured to determine current through the regeneration circuit.

8. The sense amplifier of claim 1 , further comprising:

an assisted charging circuit coupled to the output node and configured to assist the output voltage reaching the threshold voltage level.

9. The sense amplifier of claim 1 , further comprising:

an external reference control circuit configured to provide a reference signal to the sensing circuit, the sensing circuit configured to change the output voltage based on the input signal and the reference signal.

10. The sense amplifier of claim 1 , wherein the output node is coupled to an input of another sense amplifier to generate another output voltage at another output node of said another sense amplifier.

11. An electronic device comprising:

a sense amplifier comprising:

a power switch coupled between a first reference voltage source at a first voltage level and a second reference voltage source at a second voltage level lower than the first voltage level, the power switch configured to enable current to flow from the first reference voltage source to the second reference voltage source in the sense amplifier responsive to a clock signal placed in a first state;

a sensing circuit coupled in series with the power switch, the sensing circuit configured to receive an input signal and change an output voltage at an output node based on the input signal during a period between a first time at which the clock signal transitions from a second state to the first state and a second time at which the output voltage reaches a threshold voltage level;

a regeneration circuit coupled in parallel to the sensing circuit and in series with the power switch, the regeneration circuit configured to amplify the changed output voltage after the second time and before the clock signal transitions from the first state to the second state, the output voltage reaching the threshold voltage level based on the current flowing from the first reference voltage source to the second reference voltage source through the power switch; and

a self clock control circuit configured to disconnect the power switch by turning off a secondary switch responsive to the output voltage reaching a holding voltage level, the secondary switch coupled in series with the power switch, the output node coupled to an input of the self clock control circuit and an output of the self clock control circuit coupled to a control terminal of the secondary switch.

Assignments (5)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
MERGER Recorded Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
SECURITY INTEREST Recorded Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035223/0387 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2014
From: TALEGAONKAR, MRUNMAY; GONDI, SRIKANTH
To: SILICON IMAGE, INC.
Reel/Frame 032853/0154 →