Patent Assignment
Reel/Frame 036419/0792
Merger
Recorded: 2015-08-21
Pages: 15
Assignor
SILICON IMAGE, INC.
Executed: 2015-05-13
Assignee
LATTICE SEMICONDUCTOR CORPORATION
111 SW 5TH AVENUE, SUITE 700, PORTLAND, OREGON, 97204
Covered Properties
(369)
Smart Scalable Storage Switch Architecture
On Screen Displays Associated with Remote Video Source Devices
Method, Apparatus, and System for Pre-Authentication and Processing of Data Streams
Proxy Device Operation in Command and Control Network
Mechanism for Facilitating Fine-Grained Self-Refresh Control for Dynamic Memory Devices
Elements to Counter Transmitter Circuit Performance Limitations
Apparatus, System and Method for Providing Clock and Data Signaling
Full-Frame Buffer to Improve Video Performance in Low-Latency Video Communication Systems
Phase-Modulated On-Off Keying for Millimeter Wave Spectrum Control
Patent:
9,178,735 →
Application:
14/339,393 →
Messaging to Provide Data Link Integrity
Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding
Phase Detection Circuits and Methods
Network Repository for Metadata
Streaming Data Content in a Network
Application:
11/828,226 →
Publication:
US US20090028142A1
Iddq Testing of Cmos Devices
Application:
13/298,001 →
Publication:
US US20120158346A1
Method, Apparatus, and System for Simultaneously Previewing Contents from Multiple Protected Sources
Application:
12/650,357 →
Publication:
US US20110157473A1
Transmission and Handling of Three-Dimensional Video Content
Application:
12/966,194 →
Publication:
US US20110149032A1
Mechanism for Partial Encryption of Data Streams
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Method, Apparatus and System for Transitioning an Audio/Video Device Between a Source Mode and a Sink Mode
Multi-View Display System
Communication Bridging Between Devices via Multiple Bridge Elements
Conversion of Multimedia Data Streams for Use by Connected Devices
Transfer of Control Bus Signaling on Packet-Switched Network
Application:
12/950,867 →
Publication:
US US20120131245A1
Mechanism for Clock Recovery for Streaming Content Being Communicated Over a Packetized Communication Network
Application:
13/339,339 →
Publication:
US US20120182473A1
Multimedia I/O System Architecture for Advanced Digital Television
Audio and Video Data Multiplexing for Multimedia Stream Switch
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Ringing Suppression in Video Scalers
Application:
13/335,398 →
Publication:
US US20130162901A1
Surface Mountable Integrated Circuit Packaging Scheme
Application:
13/403,146 →
Mechanism for communication with multiple wireless video area networks
Application:
12/215,959 →
Publication:
US US20090086695A1
Exchanging Information Between Components Coupled with an a I2C Bus via Separate Banks
Application:
12/164,757 →
Publication:
US US20090327572A1
Dispatch Capability Using a Single Physical Interface
Bitmap Device Identification in a Wireless Communication System
High Speed Integrated Circuit Interface
Patent:
9,367,495 →
Application:
12/242,665 →
Driving Data of Multiple Protocols Through a Single Set of Pins
Combining Video and Audio Streams Utilizing Pixel Repetition Bandwidth
Compensation Scheme for Mhl Common Mode Clock Swing
Transmitting Multiple Differential Signals Over a Reduced Number of Physical Channels
Mechanism for Facilitating Cost-Efficient and Low-Latency Encoding of Video Streams
Application:
13/460,393 →
Publication:
US US20130287100A1
Configurable Single-Ended Driver
Test Solution for a Random Number Generator
Auxiliary Data Encoding in Video Data
Application:
13/787,664 →
Publication:
US US20140204994A1
Method and Apparatus for Reducing Digital Video Image Data
Application:
13/738,768 →
Publication:
US US20140152891A1
Line Driver with Separate Pre-Driver for Feed-Through Capacitance
Integrated Mobile Desktop
Multiple Protocol Tunneling Using Time Division Operations
Methods and Apparatuses to Provide an Electro-Optical Alignment
Charge Pump Calibration for Dual-Path Phase-Locked Loop
Formatting Audio-Video Information Compliant with First Transmission Format to Second Transmission Format in Integrated Circuit for Offloading Physical Layer Logic for First Transmission Format to Separate Integrated Circuit
MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA)
Application:
13/521,739 →
Publication:
US US20130191570A1
Video Management and Control in Home Multimedia Network
Linear Regulator with Improved Power Supply Ripple Rejection
Electronic Alignment of Optical Signals
Application:
13/844,152 →
Publication:
US US20140193165A1
Apparatus, System and Method for Providing Switching with a T-Coil Circuit
Apparatus, Method and System for Asymmetric, Full-Duplex Communication
Method and Apparatus for Implementing Wide Data Range and Wide Common-Mode Receivers
Transmitting Apparatus with Source Termination
Caching of Capabilities Information of Counterpart Device for Efficient Handshaking Operation
Mechanism for Facilitating Dynamic Counter Synchronization and Packetization in High-Definition Multimedia Interface and Mobile High-Definition Link
Communication of Multimedia Data Streams over Multiple Communication Lanes
Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures
Techniques for Fractional-N Phase Locked Loops
Spectrum Shaping Voltage to Current Converter
Electrical Duplex to Optical Conversion
Arbitration Signaling Within a Multimedia High Definition Link (Mhl 3) Device
Phase Locked Loop with Sub-harmonic Locking Prevention Functionality
Error Detection and Mitigation in Video Channels
Application:
14/275,692 →
Publication:
US US20150326884A1
Frequency Response Compensation in a Digital to Analog Converter
Calibration of Single-Ended High-Speed Interfaces
Compressed Video Transfer over a Multimedia Link
Application:
14/470,613 →
Publication:
US US20150256842A1
Video Frame Synchronization
Application:
14/184,647 →
Publication:
US US20140168514A1
Power Delivery Over Digital Interaction Interface for Video and Audio (DiiVA)
Inter-Device Conflict Resolution on a Multimedia Link
Phase Relationship Control for Control Channel of a Multimedia Communication Link
Retry Disparity for Control Channel of a Multimedia Communication Link
Calibration of Single-Ended High-Speed Interfaces
Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling
System and Method for Transcoding Data
Electrical Connector with Optical Channel
Application:
14/502,928 →
Publication:
US US20160091669A1
Cable with Circuitry for Communicating Performance Information
Compressed Blanking Period Transfer Over a Multimedia Link
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Radio Frequency Interference Reduction In Multimedia Interfaces
Configurable Multi-Dimensional Driver and Receiver
Calibration for Echo Cancellation in a Full Duplex Communication System
Displaying Multiple Videos on Sink Device Using Display Information of Source Device
Enhanced Communication Link Using Synchronization Signal as Link Command
Application:
14/483,013 →
Publication:
US US20160072601A1
Network Topology Discovery
Control Target Selection
System for Dynamic Audio Visual Capabilities Exchange
Method for Synchronizing A/V Streams
Media Stream Data and Control Parameter Synchronization
Stream Creation with Limited Topology Information
Adaptive Processing of Video Streams with Reduced Color Resolution
Multimedia Link Having a Plug and a Receptacle with a Power Line Configured as a Signal Return Path
Orthogonal Data Organization for Error Detection and Correction in Serial Video Interfaces
Application:
14/673,378 →
Publication:
US US20150281743A1
Detecting the Orientation of a Multimedia Link Connected to a Device
Efficient Routing of Streams Encrypted Using Point-to-Point Authentication Protocol
Bidirectional Transmission Of USB Data Using Audio/Video Data Channel
Configuring an Electronic Device Based on a Transaction
Facilitating Interactive Support Sessions for an Embedded Device Using a Portable Device
Application:
14/170,896 →
Publication:
US US20150222709A1
Bandwidth Acquisition in Contention-based Networks
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Secure Control Communication Between an Application Processor and a Transmitter
Application:
62/061,630 →
Secure Internal Control for Encrypting Video Data
Stream Creation with Limited Topology Information
Stream Creation with Limited Topology Information
Port Processor Capable of Performing Authentication for Multiple Source Devices
Metadata Transfer for HDMI/MHL
Application:
62/075,554 →
Low Power Operations in a Wireless Tunneling Transceiver
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
HDMI Connector
High-bandwidth Digital Content Protection over Audio Return Channel
Application:
62/089,767 →
Enhanced Echo Cancellation in Full-Duplex Communication
I/Q Imbalance Correction for the Combination of Multiple Radio Frequency Frontends
Application:
62/100,841 →
Multi-Antenna Transmitter for Multi-Tone Signaling
Directional Beam Steering System and Method to Detect Location and Motion
Methods and Systems for Near-Field MIMO Communications
Integrated Phase-Shifting-and-Combining Circuitry to Support Multiple Antennas
High-Accuracy and Low-Power Tracking System for Mobile Devices
Low-Cost Tracking System
Calibrating a Retro-Directive Array for an Asymmetric Wireless Link
Collaborative Channel Sounding in Multi-Antenna Systems
High-Accuracy Detection in Collaborative Tracking Systems
Antenna Selection and Pilot Compression in Mimo Systems
Wireless Tunneling System
Application:
62/135,007 →
Single-Ended Configurable Multi-Mode Driver
Communication Using Continuous-Phase Modulated Signals
Tracking System with Orthogonal Polarizations and a Retro-Directive Array
Communicating Sliced Sideband Data with Video Data
Application:
62/168,169 →
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
System and Method for Driving Columns of an Active Matrix Display
Patent:
6,157,360 →
Application:
08/815,486 →
Voltage-Controlled Oscillator Resistant to Supply Voltage Noise
Patent:
5,955,929 →
Application:
08/920,336 →
Dual Loop Delay-Locked Loop
Patent:
5,969,552 →
Application:
09/007,707 →
Transition-Controlled Digital Encoding and Signal Transmission System
Patent:
5,825,824 →
Application:
08/622,810 →
Scaling Multi-Dimensional Signals Using Variable Weighting Factors
Patent:
6,259,427 →
Application:
09/298,647 →
System and Method for High-Speed, Synchronized Data Communication
Patent:
6,229,859 →
Application:
09/146,818 →
System and Method for High-Speed, Synchronized Data Communication
Skew-Insensitive Low Voltage Differential Receiver
Patent:
6,374,361 →
Application:
09/298,369 →
Method and Apparatus for Bidirectional Data Transfer Between a Digital Display and a Computer
Patent:
6,738,417 →
Application:
09/393,849 →
Display Module Driving System and Digital to Analog Converter for Driving Display
Patent:
6,940,496 →
Application:
09/326,503 →
Bi-Directional Data Transfer Using the Video Blanking Period in a Digital Data Stream
Patent:
6,564,269 →
Application:
09/392,229 →
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Patent:
6,307,543 →
Application:
09/393,234 →
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Baud-Rate Timing Recovery
Wide frequency-range delay-locked loop circuit
Patent:
6,326,826 →
Application:
09/574,571 →
Methods and Systems for Sending Side-Channel Data During Data Inactive Period
Patent:
6,954,491 →
Application:
09/881,271 →
Digital Display Jitter Correction Apparatus and Method
Digital Display Jitter Correction Apparatus and Method
Multi-Phase Voltage Controlled Oscillator (Vco) with Common Mode Control
Patent:
6,717,478 →
Application:
09/989,587 →
Data Synchronization Across an Asynchronous Boundary Using, for Example, Multi-Phase Clocks
Bidirectional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Patent:
7,103,013 →
Application:
09/989,580 →
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Memory Architecture with Multiple Serial Communications Ports
Communications Architecture for Transmission of Data Between Memory Bank Caches and Ports
Digital Video System and Methods for Providing Same
Patent:
6,380,978 →
Application:
09/167,527 →
Digital Video System and Methods for Providing Same
Portable Dvd Player
Method and Apparatus for Deinterlacing Digital Video Images
Patent:
6,489,998 →
Application:
09/372,713 →
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Method and Apparatus for Deinterlacing Digital Video Images
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Method and Apparatus for Detecting Frequency in Digital Video Images
Interlace Motion Artifact Detection Using Vertical Frequency Detection and Analysis
Method and Apparatus for Detecting the Source Format of Video Images
Method and Apparatus for Detecting and Smoothing Diagonal Features Video Images
Patent:
6,515,706 →
Application:
09/396,993 →
Method and Apparatus for Detecting and Smoothing Diagonal Features in Video Images
Method and Apparatus for Efficient Video Scaling
Patent:
6,681,059 →
Application:
09/363,312 →
Method and Apparatus for Reducing on-Chip Memory in Vertical Video Processing
Patent:
6,587,158 →
Application:
09/359,530 →
Methods and Apparatus for Variable Length Sdram Transfers
Patent:
6,219,747 →
Application:
09/226,776 →
Methods and Apparatus for Variable Length Sdram Transfers
Methods and Apparatus for Data Bus Arbitration
Patent:
6,393,505 →
Application:
09/227,502 →
Method and Apparatus for Providing Deterministic Resets for Clock Divider Systems
Patent:
6,473,476 →
Application:
09/226,381 →
Method, System and Article of Manufacture for Identifying the Source Type and Quality Level of a Video Sequence
Audio Signal Delay Apparatus and Method
Patent:
7,203,557 →
Application:
09/478,122 →
Detection and Repair of Mpeg-2 Chroma Upconversion Artifacts
Clock Jitter Limiting Scheme in Video Transmission Through Multiple Stages
Patent:
7,123,307 →
Application:
09/905,318 →
System and Method for Measuring Pseudo Pixel Error Rate
Patent:
6,944,804 →
Application:
09/905,615 →
Method of Testing Serial Interface
Patent:
6,625,560 →
Application:
09/904,783 →
High-Speed Bus with Embedded Clock Signals
Patent:
6,845,461 →
Application:
09/989,590 →
System and Method for Multiple-Phase Clock Generation
Patent:
6,809,567 →
Application:
09/989,645 →
Method and Apparatus for Adaptive Control of Pll Loop Bandwidth
Patent:
7,062,004 →
Application:
09/905,511 →
Deinterlacing of Video Sources via Image Feature Edge Detection
Patent:
7,023,487 →
Application:
10/057,823 →
Method and Apparatus for Sending Auxiliary Data on a Tmds-Like Link
Patent:
7,558,326 →
Application:
09/954,663 →
Encoding Method and System for Reducing Inter-Symbol Interference Effects in Transmission Over a Serial Link
Method and System for Reducing Inter-Symbol Interference Effects in Transmission Over a Serial Link with Mapping of Each Word in a Cluster of Received Words to a Single Transmitted Word
Method and Apparatus for Regenerating a Clock for Auxiliary Data Transmitted Over a Serial Link with Video Data
Patent:
7,088,398 →
Application:
10/171,860 →
Method and System for Video and Auxiliary Data Transmission Over a Serial Link
Patent:
6,914,637 →
Application:
10/192,296 →
Method and Circuit for Generating Time Stamp Data from an Embedded-Clock Audio Data Stream and a Video Clock
Method and System for Spatial-Temporal Dithering for Displays with Overlapping Pixels
Patent:
6,714,206 →
Application:
10/016,247 →
Cryptosystems Using Commuting Pairs in a Monoid
Patent:
7,136,484 →
Application:
10/133,813 →
Supporting Circuitry and Method for Controlling Pixels
Patent:
7,109,958 →
Application:
10/047,772 →
Method and System for Transition-Controlled Selective Block Inversion Communications
Enclosure for Removable Computer Peripheral Equipment
Patent:
6,018,456 →
Application:
08/656,032 →
System and Method for Interfacing Manually Controllable Input Devices to a Universal Computer Bus System
Patent:
5,991,546 →
Application:
08/906,775 →
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Patent:
7,225,282 →
Application:
10/171,820 →
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Method and System for Arbitrating Priority Bids Sent Over Serial Links to a Multi-Port Storage Device
Patent:
7,171,525 →
Application:
10/210,839 →
Cyclic phase signal generation from a single clock source using current phase interpolation
Patent:
6,380,783 →
Application:
09/688,536 →
Fully Differential Continuous-Time Current-Mode High Speed Cmos Comparator
Voltage Swing Detection Circuit for Hot Plug Event or Device Detection via a Differential Link
Patent:
7,009,827 →
Application:
10/270,882 →
Method and Apparatus for Connecting Serial Ata Storage Components
Patent:
6,843,674 →
Application:
10/162,046 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Patent:
7,131,004 →
Application:
09/945,278 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
System and Method for an Adaptive State Machine to Control Signal Filtering in a Serial Link
Patent:
7,218,737 →
Application:
10/224,995 →
Method and System for Encrypting and Decrypting Data Using an External Agent
Patent:
7,242,766 →
Application:
09/991,057 →
Method and System for Temporary Interruption of Video Data Transmission
Patent:
7,035,290 →
Application:
10/085,177 →
Method and System for Host Handling of Communications Errors
Method and System for Communicating Control Information via Out-of-Band Symbols
Method and System for Integrating Packet Type Information with Synchronization Symbols
Method and System for Nesting of Communications Packets
Method and System for Dc-Balancing at the Physical Layer
Patent:
6,771,192 →
Application:
10/045,600 →
Multisection Memory Bank System
Logic Gates Including Diode-Connected Metal-Oxide-Semiconductor Field-Effect Transistors (Mosfets) to Control Input Threshold Voltage Levels and Switching Transients of Output Logic Signals
Patent:
7,058,121 →
Application:
09/989,647 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Patent:
6,985,005 →
Application:
09/989,487 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Transmitter and Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers to Suppress Noise
Continuous-Time, Low-Frequency-Gain/High-Frequency-Boosting Joint Adaptation Equalizer and Method
Patent:
6,819,166 →
Application:
10/403,477 →
Video/Graphics Text Mode Enhancement Method for Digitally Processed Data
Patent:
7,348,991 →
Application:
10/417,712 →
Detection of Video Windows and Graphics Windows
Patent:
6,873,341 →
Application:
10/287,976 →
Integrated Circuit Having Self Test Capability Using Message Digest and Method for Testing Integrated Circuit Having Message Digest Generation Circuitry
Patent:
7,539,304 →
Application:
10/298,722 →
Dynamically Biased Full-Swing Operation Amplifier for an Active Matrix Liquid Crystal Display Driver
Patent:
6,717,468 →
Application:
10/215,936 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,412,053 →
Application:
10/268,832 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,797,536 →
Application:
11/950,088 →
Through-Board Pcb Edge Connector, System and Method
Patent:
6,814,583 →
Application:
10/244,152 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Patent:
8,064,508 →
Application:
10/247,675 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Cmos Transceiver with Dual Current Path Vco
Patent:
7,551,909 →
Application:
10/651,500 →
Data Sampling Method and Apparatus with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization
Patent:
7,409,031 →
Application:
10/642,259 →
Method and System for Encapsulation of Multiple Levels of Communication Protocol Functionality Within Line Codes
Patent:
7,187,307 →
Application:
10/459,989 →
Method and Circuit for Adaptive Equalization of Multiple Signals in Response to a Control Signal Generated from One of the Equalized Signals
Method and Apparatus for Encoding or Decoding Data in Accordance with an Nb/(N+1)B Block Code, and Method for Determining Such a Block Code
Patent:
6,747,580 →
Application:
10/459,992 →
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Apparatus for Removably Securing Storage Components in an Enclosure
Reduced Dead-Cycle, Adaptive Phase Tracking Method and Apparatus
Patent:
7,236,553 →
Application:
10/763,905 →
Method and Apparatus for Run Length Limited Tmds-Like Encoding of Data
Patent:
6,897,793 →
Application:
10/835,301 →
Data Sampling Method and Apparatus Using Through-Transition Counts to Reject Worst Sampling Position
Patent:
7,991,096 →
Application:
10/842,231 →
Method and Circuit for Dc Measurement of Phase Uniformity of Multi-Phase Clocks
Patent:
7,031,858 →
Application:
10/439,446 →
Age Selection Switching Scheme for Data Traffic in a Crossbar Switch
Patent:
7,274,690 →
Application:
10/302,436 →
Preference Programmable First-One Detector and Quadrature Based Random Grant Generator
Patent:
7,505,422 →
Application:
10/645,786 →
Method for Multicast Service in a Crossbar Switch
Patent:
7,461,167 →
Application:
10/645,787 →
Content Addressable Merged Queue Architecture for Switching Data
Patent:
7,352,764 →
Application:
10/762,950 →
Method for Switching Data in a Crossbar Switch
Patent:
7,519,066 →
Application:
10/434,785 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Parallel Interface Bus to Communicate Video Data Encoded for Serial Data Links
Phase Lock Loop with Coarse Control Loop Having Frequency Lock Detector and Device Including Same
Patent:
7,102,446 →
Application:
11/056,995 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Current Mode Circuitry to Modulate a Common Mode Voltage
Test Clock Control Structures to Generate Configurable Test Clocks for Scan-Based Testing of Electronic Circuits Using Programmable Test Clock Controllers
Parameter Scanning for Signal Over-Sampling
Determining Oversampled Data to Be Included in Unit Intervals
Smart scalable storage switch architecture
Covert Channel for Conveying Supplemental Messages in a Protocol-Defined Link for a System of Storage Devices
Adaptive Bandwidth Phase Locked Loop with Feedforward Divider
Concurrent Code Checker and Hardware Efficient High-Speed I/O Having Built-in Self-Test and Debug Features
Inter-Port Communication in a Multi-Port Memory Device
Multi-Port Memory Device Having Variable Port Speeds
Shared Nonvolatile Memory Architecture
Scan-Based Testing of Devices Implementing a Test Clock Control Structure ("Tccs")
Signal Interleaving for Serial Clock and Data Recovery
Progressive Power Control of a Multi-Port Memory Device
Interface Test Circuitry and Methods
Ensuring Physical Locality of Entities Sharing Data
Circuitry to Prevent Peak Power Problems During Scan Shift
Power-Saving Clocking Technique
Method of Context Adaptive Binary Arithmetic Coding and Coding Apparatus Using the Same
Patent:
7,365,659 →
Application:
11/567,514 →
Method for Coding Video Data
Patent:
6,078,692 →
Application:
09/009,905 →
Multi-Level Port Expansion for Port Multipliers
Operation of Media Interface to Provide Bidirectional Communications
Delivering on Screen Display Data to Existing Display Devices
On Screen Displays Associated with Remote Video Source Devices
Bandwidth Reservation for Data Flows in Interconnection Networks
Data Stream Control for Network Devices
Automated Service Discovery and Dynamic Connection Management
Network Repository for Metadata
Packet Level Prioritization in Interconnection Networks
Synchronizing Related Data Streams in Interconnection Networks
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Method, Apparatus, and System for Port Multiplier Enhancement
Method, Apparatus, and System for Employing an Enhanced Port Multiplier
Computer Memory Test Structure
Computer Memory Test Structure
Computer Memory Test Structure
Group Power Management of Network Devices
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Method, Apparatus and System for Generating and Facilitating Mobile High-Definition Multimedia Interface
Control Bus for Connection of Electronic Devices
Discovery of Electronic Devices Utilizing a Control Bus
Methods and Mechanisms for Probabilistic Color Correction
Method, Apparatus, and System for Deciphering Media Content Stream
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Method, Apparatus, and System for Automatic Data Aligner for Multiple Serial Receivers
Fault Testing for Interconnections
Detection of Encryption Utilizing Error Detection for Received Data
Messaging to Provide Data Link Integrity
Coding System for Memory Systems Employing High-Speed Serial Links
17B/20B Coding System
Method, Apparatus, and System for Pre-Authentication and Keep-Authentication of Content Protected Ports
Method, Apparatus and System for Employing a Content Protection System
Discovery of Connections Utilizing a Control Bus
Transmission of Alternative Content Over Standard Device Connectors
Method and System for Detecting Successful Authentication of Multiple Ports in a Time-Based Roving Architecture
Signaling for Transitions Between Modes of Data Transmission
Adaptive Interconnection Scheme for Multimedia Devices
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Video Frame Synchronization
De-Encapsulation of Data Streams into Multiple Links
Hybrid Interface for Serial and Parallel Communication
Hybrid Interface for Serial and Parallel Communication
Mechanism for Internal Processing of Content Through Partial Authentication on Secondary Channel
Testing of High-Speed Input-Output Devices
Multi-View Display System
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Combining Video Data Streams of Differing Dimensionality for Concurrent Display
Detection of Cable Connections for Electronic Devices
Detection of Cable Connections for Electronic Devices
Mechanism for Low Power Standby Mode Control Circuit
Conversion and Processing of Deep Color Video in a Single Clock Domain
Mechanism for Facilitating a Configurable Port-Type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment Host Controller Architecture
Discovery of Electronic Devices in a Combined Network
Discovery of Electronic Devices in a Combined Network
Single-Ended Configurable Multi-Mode Driver
Configurable Multi-Dimensional Driver and Receiver
Adjustment of Clock Signals Regenerated from a Data Stream
Edge Detection
Edge Detection
Video Stream Routing and Format Conversion Unit with Audio Delay
Patent:
7,400,359 →
Application:
10/753,909 →
Time Base Correction and Frame Rate Conversion
Patent:
7,710,501 →
Application:
10/889,855 →
Original Scan Line Detection
Noise Cancellation
Source-Adaptive Video Deinterlacer
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Block Noise Detection and Filtering
Block Noise Detection and Filtering
Transmission of Multiple Protocol Data Elements via an Interface Utilizing a Data Tunnel
Identification and Handling of Data Streams Using Coded Preambles
Mechanism for Facilitating Synchronization of Audio and Video Between Multiple Media Devices
Interfacing Between Integrated Circuits with Asymmetric Voltage Swing
Integrated Connector/Flex Cable
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Test Solution for Ring Oscillators
Mechanism for Facilitating Dynamic Timestamp-Less Clock Generation for Transmitting Media Streams Over Shared Channels
Method, Apparatus and System for Communicating Sideband Data with Non-Compressed Video
Patent:
8,786,776 →
Application:
13/891,842 →
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Integration of Signal Sampling Within Transistor Amplifier Stage
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Multi-Antenna Transmitter for Multi-Tone Signaling
Multi-Antenna Beam-Forming System for Transmitting Constant Envelope Signals Decomposed from a Variable Envelope Signal
Communication Using Continuous-Phase Modulated Signals
Communication Using Continuous-Phase Modulated Signals
Technique for Determining an Angle of Arrival in a Communication System
Antenna Array with Flexible Interconnect for a Mobile Wireless Device
Transforming Signals Using Passive Circuits
Technique for Low-Power Operation of a Wireless Device
Displacement Sensing Using a Flexible Substrate
Signal Distribution Networks and Related Methods
Signal Distribution Networks and Related Methods
Directional Beam Steering System and Method to Detect Location and Motion
Tracking System with Orthogonal Polarizations and a Retro-Directive Array
Related Assignments
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Assignment of Assignor's Interest
Mar 24, 2011
From: WONG, JASON; KIM, GYUDONG
To: SILICON IMAGE, INC.
Reel/Frame 026016/0133 →
Assignment of Assignor's Interest
Jun 26, 2012
From: ARYANFAR, FARSHID; LEE, HAE-CHANG; WERNER, CARL
To: RAMBUS INC.
Reel/Frame 028447/0805 →
Assignment of Assignor's Interest
Aug 7, 2013
From: AGRAWAL, VINAYAK; SHARMA, NAMRTA; RAMAPURAM, DEEPAK
To: SILICON IMAGE, INC.
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Assignment of Assignor's Interest
May 27, 2014
From: CHOI, HOON; THOMPSON, LAURENCE A
To: SILICON IMAGE, INC.
Reel/Frame 032970/0048 →
Assignment of Assignor's Interest
Aug 11, 2014
From: HO, RICKY KEANGPO; CHENG, SHI
To: SILICON IMAGE, INC.
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Assignment of Assignor's Interest
Jan 23, 2015
From: RAMBUS INC.
To: SILICON IMAGE, INC.
Reel/Frame 034807/0001 →
Assignment of Assignor's Interest
Mar 6, 2015
From: RAMBUS INC.
To: SILICON IMAGE, INC.
Reel/Frame 035141/0390 →
Security Interest
Mar 17, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
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Security Interest
Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
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Mar 19, 2015
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To: JEFFERIES FINANCE LLC
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Security Interest
Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
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Assignment of Assignor's Interest
Aug 12, 2015
From: NORTHCUTT, J. DUANE; HANKO, JAMES G.; SCHMIDT, BRIAN K.
To: SILICON IMAGE, INC.
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To: LATTICE SEMICONDUCTOR CORPORATION
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Merger
Aug 14, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
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From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
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Assignment of Assignor's Interest
Mar 7, 2017
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.
To: QUALCOMM INCORPORATED
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Release of Security Interest
Mar 7, 2017
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To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
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Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
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Release of Security Interest
May 21, 2019
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To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
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Release of Security Interest
Nov 10, 2021
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To: LATTICE SEMICONDUCTOR CORPORATION
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Assignment of Assignor's Interest
Dec 16, 2021
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To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
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