Mechanism for facilitating a configurable port-type peripheral component interconnect express/serial advanced technology attachment host controller architecture
View Patent ↗A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.
1. An apparatus comprising:
a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports;
at least one pin to be strapped before power is applied to the apparatus; and
logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports based on the strapping of the at least one pin.
2. The apparatus of claim 1 , further comprising a single switch to trigger the logic to facilitate swapping between a PCIe port and a SATA port.
3. The apparatus of claim 1 , further comprising multiple switches to trigger the logic to facilitate swapping between the PCIe port and the SATA port.
4. The apparatus of claim 1 , wherein the plurality of PHYs include 16 PHYs having a combination of 1 PCIe port and 15 SATA ports.
5. The apparatus of claim 1 , wherein the plurality of PHYs include 16 PHYs having a combination of 2 PCIe ports and 14 SATA ports.
6. The apparatus of claim 1 , wherein the plurality of PHYs include 16 PHYs having a combination of 4 PCIe ports and 12 SATA ports.
7. The apparatus of claim 1 , wherein the plurality of PHYs include 16 PHYs having a combination of 8 PCIe ports and 8 SATA ports.
8. A system comprising:
an integrated circuit having:
a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports;
at least one pin to be strapped before power is applied to the integrated circuit; and
logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports based on the strapping of the at least one pin.
9. The system of claim 8 , further comprising a single switch to trigger the logic to facilitate swapping between a PCIe port and a SATA port.
10. The system of claim 8 , further comprising multiple switches to trigger the logic to facilitate swapping between the PCIe port and the SATA port.
11. The system of claim 8 , wherein the plurality of PHYs include 16 PHYs having a combination of 1 PCIe port and 15 SATA ports.
12. The system of claim 8 , wherein the plurality of PHYs include 16 PHYs having a combination of 2 PCIe ports and 14 SATA ports.
13. The system of claim 8 , wherein the plurality of PHYs include 16 PHYs having a combination of 4 PCIe ports and 12 SATA ports.
14. The system of claim 8 , wherein the plurality of PHYs include 16 PHYs having a combination of 8 PCIe ports and 8 SATA ports.
15. A method comprising:
identifying a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports;
strapping at least one pin before power is applied; and
swapping one or more of the plurality of PHYs between being the PCIe ports and the SATA ports based on the strapping of the at least one pin.
16. The method of claim 15 , further comprising swapping between a PCIe port and a SATA port using a single switch.
17. The method of claim 15 , further comprising swapping between the PCIe port and the SATA port using multiple switches.
18. The method of claim 15 , wherein the plurality of PHYs include 16 PHYs having a combination of 1 PCIe port and 15 SATA ports.
19. The method of claim 15 , wherein the plurality of PHYs include 16 PHYs having a combination of 2 PCIe ports and 14 SATA ports.
20. The method of claim 15 , wherein the plurality of PHYs include 16 PHYs having a combination of 4 PCIe ports and 12 SATA ports, and wherein the plurality of PHYs include 16 PHYs having a combination of 8 PCIe ports and 8 SATA ports.