Patent Assignment
Reel/Frame 049795/0481
Security Interest
Recorded: 2019-07-18
Pages: 11
Assignor
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2019-07-18
Assignee
WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
1700 LINCOLN STREET, 3RD FLOOR, MAC C7300-033, DENVER, COLORADO, 80203-4500
Covered Properties
(73)
Line Driver Apparatus with Combined Feed-Through Capacitance and Feed-Forward Equalization
Replica Cascode Bias Voltage-Controlled Oscillators
Optical Connectors and Related Manufacturing Techniques
Application:
15/682,478 →
Publication:
US US20170343744A1
Methods and Devices for Data Demodulation
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Patent:
6,307,543 →
Application:
09/393,234 →
Wide frequency-range delay-locked loop circuit
Patent:
6,326,826 →
Application:
09/574,571 →
Bi-Directional Data Transfer Using Two Pair of Differential Lines as a Single Additional Differential Pair
Bi-Directional Data Transfer Using the Video Blanking Period in a Digital Data Stream
Patent:
6,564,269 →
Application:
09/392,229 →
Multi-Phase Voltage Controlled Oscillator (Vco) with Common Mode Control
Patent:
6,717,478 →
Application:
09/989,587 →
Method and Apparatus for Bidirectional Data Transfer Between a Digital Display and a Computer
Patent:
6,738,417 →
Application:
09/393,849 →
Baud-Rate Timing Recovery
Display Module Driving System and Digital to Analog Converter for Driving Display
Patent:
6,940,496 →
Application:
09/326,503 →
Methods and Systems for Sending Side-Channel Data During Data Inactive Period
Patent:
6,954,491 →
Application:
09/881,271 →
Digital Display Jitter Correction Apparatus and Method
Bidirectional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Patent:
7,103,013 →
Application:
09/989,580 →
Method and System for Nesting of Communications Packets
Method and System for Encapsulation of Multiple Levels of Communication Protocol Functionality Within Line Codes
Patent:
7,187,307 →
Application:
10/459,989 →
Data Synchronization Across an Asynchronous Boundary Using, for Example, Multi-Phase Clocks
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Method and Circuit for Generating Time Stamp Data from an Embedded-Clock Audio Data Stream and a Video Clock
Data Sampling Method and Apparatus with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization
Patent:
7,409,031 →
Application:
10/642,259 →
Determining Oversampled Data to Be Included in Unit Intervals
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Cmos Transceiver with Dual Current Path Vco
Patent:
7,551,909 →
Application:
10/651,500 →
Digital Display Jitter Correction Apparatus and Method
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Passive Equalizer with Negative Impedance to Increase a Gain
Parameter Scanning for Signal Over-Sampling
Control Bus for Connection of Electronic Devices
Adaptive Equalizer for Use with Clock and Data Recovery Circuit of Serial Communication Link
Discovery of Electronic Devices Utilizing a Control Bus
Method, Apparatus, and System for Automatic Data Aligner for Multiple Serial Receivers
Method, Apparatus and System for Generating and Facilitating Mobile High-Definition Multimedia Interface
Bi-Directional Bridge Circuit Having High Common Mode Rejection and High Input Sensitivity
Transmission of Alternative Content Over Standard Device Connectors
Discovery of Connections Utilizing a Control Bus
Conversion and Processing of Deep Color Video in a Single Clock Domain
Detection of Cable Connections for Electronic Devices
Detection of Cable Connections for Electronic Devices
Adjustment of Clock Signals Regenerated from a Data Stream
Integrated Connector/Flex Cable
Cable with Circuitry for Communicating Performance Information
Multimedia Link Having a Plug and a Receptacle with a Power Line Configured as a Signal Return Path
Cable with Circuitry for Communicating Performance Information
Reversible Receptacle Connector
Patent:
9,472,873 →
Application:
14/824,717 →
Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling
Calibration for Echo Cancellation in a Full Duplex Communication System
Detecting the Orientation of a Multimedia Link Connected to a Device
Enhanced Echo Cancellation in Full-Duplex Communication
Calibration for Echo Cancellation in a Full Duplex Communication System
Method, Apparatus, and System for Port Multiplier Enhancement
Scan-Based Testing of Devices Implementing a Test Clock Control Structure ("Tccs")
Circuitry to Prevent Peak Power Problems During Scan Shift
Test Clock Control Structures to Generate Configurable Test Clocks for Scan-Based Testing of Electronic Circuits Using Programmable Test Clock Controllers
Apparatus for Removably Securing Storage Components in an Enclosure
Zero-Power Programmable Memory Cell
Patent:
40,311 →
Application:
11/206,282 →
Transmitter Circuit Harvesting Power from Power Supply of a Receiver Circuit
Power Delivery Over Digital Interaction Interface for Video and Audio (DiiVA)
Computer Memory Test Structure
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Mechanism for Facilitating a Configurable Port-Type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment Host Controller Architecture
Testing of High-Speed Input-Output Devices
Multi-Level Port Expansion for Port Multipliers
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Computer Memory Test Structure
Method, Apparatus, and System for Employing an Enhanced Port Multiplier
Operation of Media Interface to Provide Bidirectional Communications
Variable Grain Architecture for Fpga Integrated Circuits
Methods and Apparatus for Variable Length Sdram Transfers
Method and Apparatus for Synchronizing Auxiliary Data and Video Data Transmitted Over a Tmds-Like Link
Patent:
7,295,578 →
Application:
09/954,291 →
Method and System for Transmiting N-Bit Video Data Over a Serial Link
Auxiliary Data Transmitted Within a Display's Serialized Data Stream
Method and System for Transmitting or Receiving N-Bit Video Data Over a Serial Link
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 12, 2003
From: SCHMIDT, BRIAN K.; HANKO, JAMES G.; NORTHCUTT, J. DUANE; RUBERG, ALAN T.
To: SILICON IMAGE, INC.
Reel/Frame 014174/0541 →
Assignment of Assignor's Interest
Feb 26, 2015
From: SHIN, YESHIK
To: SILICON IMAGE, INC.
Reel/Frame 035044/0324 →
Security Interest
Mar 17, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035220/0226 →
Security Interest
Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0147 →
Security Interest
Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0289 →
Merger
Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
Release of Security Interest
Oct 28, 2015
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036905/0327 →
Assignment of Assignor's Interest
Aug 1, 2016
From: LUO, KEXIN; YIN, RUI; WANG, XIAOFENG; YUAN, JIE
To: SILICON IMAGE, INC.
Reel/Frame 039308/0468 →
Merger
Aug 1, 2016
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 039308/0463 →
Assignment of Assignor's Interest
Jan 25, 2017
From: WU, QIMING; ZHANG, BING; SONG, FEI
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 041082/0583 →
Assignment of Assignor's Interest
Aug 21, 2017
From: KIM, KIHONG
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 043349/0128 →
Assignment of Assignor's Interest
Aug 30, 2017
From: LUO, KEXIN
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 043447/0352 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Assignment of Assignor's Interest
Sep 9, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: KONINKLIJKE PHILIPS N.V.
Reel/Frame 050314/0434 →
Release of Security Interest
Nov 10, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 058067/0896 →
Assignment of Assignor's Interest
Dec 16, 2021
From: LATTICE SEMICONDUCTOR CORPORATION
To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
Reel/Frame 058979/0440 →
Security Interest
Sep 1, 2022
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 061365/0560 →