Circuitry to prevent peak power problems during scan shift

1. A chip comprising:

first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during capture periods; and

circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal;

wherein the circuitry to provide the first and second test clock signals includes:

a first test clock circuit including a first delay circuit and a first multiplexer to pass a first delay clock signal as the first test clock signal during the scan input periods, the first delayed clock signal being a scan shift clock signal delayed by at least the first delay circuit, and pass a first capture clock signal as the first test clock signal during the capture periods; and

a second test clock circuit coupled with the first test circuit including a second delay circuit and a second multiplexer to pass a second delayed signal as the second test clock signal during the scan input periods, the second delayed clock signal being the first delayed clock signal from the first test clock circuit delayed additionally by at least the second delay circuit, and pass a second capture clock signal as the second test clock during the capture periods.

2. The chip of claim 1 , wherein the first and second test clock circuits include the first and second delay circuits at the outputs of the first and second multiplexers to delay the first and second test clock signals prior to their being provided to the registers of the first and second scan chain segments, respectively.

3. The chip of claim 1 , wherein the scan shift clock signal and the first and second signal capture clock signals originate from a common signal.

4. The chip of claim 1 , wherein:

the first test circuit further includes a third multiplexor to pass an output signal to the first multiplexor and a third delay circuit, wherein the third multiplexor is configurable to connect the third delay circuit in series with the first delay circuit to additionally delay the scan shift clock signal by the third delay circuit; and

the second test circuit further includes a fourth multiplexor to pass an output signal to the second multiplexor and a fourth delay circuit, wherein the fourth multiplexor is configurable to connect the fourth delay circuit in series with the second delay circuit to additionally delay the first delayed clock signal by the fourth delay circuit.

5. The chip of claim 1 , further comprising additional test clock circuits to provide additional test clock signals to additional scan chain segments including a third test clock circuit, and wherein an output of the second scan chain segment is connected to an input of the third scan chain segment.

6. A chip comprising:

first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during capture periods; and

circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is skewed with respect to the first test clock signal during the scan input periods, and the first and second test clock signals are aligned during the capture periods;

wherein the circuitry to provide the first and second test clock signals includes:

a first test clock circuit including a first delay circuit and a first multiplexer to pass a first delay clock signal as the first test clock signal during the scan input periods, the first delayed clock signal being a scan shift clock signal delayed by at least the first delay circuit, and pass a first capture clock signal as the first test clock signal during the capture periods; and

a second test clock circuit coupled with the first test circuit including a second delay circuit and a second multiplexer to pass a second delayed signal as the second test clock signal during the scan input periods, the second delayed clock signal being the first delayed clock signal from the first test clock circuit delayed additionally by at least the second delay circuit, and pass a second capture clock signal as the second test clock during the capture periods.

7. The chip of claim 6 , wherein the first and second test clock circuits include the first and second delay circuits at the outputs of the first and second multiplexers to delay the first and second test clock signals prior to their being provided to the registers of the first and second scan chain segments, respectively.

8. The chip of claim 6 , wherein:

the first test circuit further includes a third multiplexor to pass an output signal to the first multiplexor and a third delay circuit, wherein the third multiplexor is configurable to connect the third delay circuit in series with the first delay circuit to additionally delay the scan shift clock signal by the third delay circuit; and

the second test circuit further includes a fourth multiplexor to pass an output signal to the second multiplexor and a fourth delay circuit, wherein the fourth multiplexor is configurable to connect the fourth delay circuit in series with the second delay circuit to additionally delay the first delayed clock signal by the fourth delay circuit.

9. A system comprising:

a chip including first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during capture periods, and circuitry such that:

(1) the circuitry provides first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is skewed with respect to the first test clock signal during the scan input periods, and the first and second test clock signals are aligned during the capture periods, and

(2) the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods; and

a tester coupled to the chip to receive signals related to the captured output signals;

wherein the circuitry includes:

a first test clock circuit including a first delay circuit and a first multiplexer to pass a first delay clock signal as the first test clock signal during the scan input periods, the first delayed clock signal being a scan shift clock signal delayed by at least the first delay circuit, and pass a first capture clock signal as the first test clock signal during the capture periods; and

a second test clock circuit coupled with the first test circuit including a second delay circuit and a second multiplexer to pass a second delayed signal as the second test clock signal during the scan input periods, the second delayed clock signal being the first delayed clock signal from the first test clock circuit delayed additionally by at least the second delay circuit, and pass a second capture clock signal as the second test clock during the capture periods.

10. The system of claim 9 , wherein the chip includes a test pattern generator to generate the scan chain input signals and analyzing circuitry to analyze the captured output signals.

11. The system of claim 9 , wherein the tester includes a test pattern generator to generate the scan chain input signals, and analyzing circuitry to analyze the signals related to the captured output signals.

12. A method comprising:

producing a first test clock signal through a first test clock circuit by either:

producing a first delayed signal during scan input periods, the first delayed signal being produced by delaying a scan shift clock through at least a first delay circuit, or

passing a capture clock signal during capture periods;

producing a second test clock signal through a second test clock circuit by either;

producing a second delayed signal during scan input periods, the second delayed signal being produced by delaying the first delayed signal additionally through at least a second delay circuit, or

passing the capture clock signal during capture periods;

providing the first test clock signal to registers of a first scan chain segment; and

providing the second test clock signal to registers of a second scan chain segment.

13. The method of claim 12 , wherein the second test clock signal is skewed with respect to the first test clock signal during scan input periods, and the first and second test clock signals are aligned during capture periods.

14. The method of claim 12 , wherein the second test clock signal is provided by a different signal path in the second test clock circuit during the scan input periods than during capture periods, and during scan input periods the second test clock signal is skewed with respect to the first test clock signal.

15. The method of claim 12 , wherein producing the first delayed signal further includes delaying the scan shift clock additionally through a third delay circuit.

16. The method of claim 15 , wherein producing the second delayed signal further includes delaying the first delayed signal additionally through a fourth delay circuit.