Patent Assignment
Reel/Frame 035226/0147
Security Interest
Recorded: 2015-03-19
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(101)
Smart Scalable Storage Switch Architecture
Multi-Level Port Expansion for Port Multipliers
On Screen Displays Associated with Remote Video Source Devices
Network Repository for Metadata
Streaming Data Content in a Network
Application:
11/828,226 →
Publication:
US US20090028142A1
Iddq Testing of Cmos Devices
Application:
13/298,001 →
Publication:
US US20120158346A1
Method and Circuit for Generating Time Stamp Data from an Embedded-Clock Audio Data Stream and a Video Clock
Method and System for Spatial-Temporal Dithering for Displays with Overlapping Pixels
Patent:
6,714,206 →
Application:
10/016,247 →
Cryptosystems Using Commuting Pairs in a Monoid
Patent:
7,136,484 →
Application:
10/133,813 →
Supporting Circuitry and Method for Controlling Pixels
Patent:
7,109,958 →
Application:
10/047,772 →
Method and System for Transition-Controlled Selective Block Inversion Communications
Enclosure for Removable Computer Peripheral Equipment
Patent:
6,018,456 →
Application:
08/656,032 →
System and Method for Interfacing Manually Controllable Input Devices to a Universal Computer Bus System
Patent:
5,991,546 →
Application:
08/906,775 →
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Patent:
7,225,282 →
Application:
10/171,820 →
Method and Apparatus for a Two-Wire Serial Command Bus Interface
Method and System for Arbitrating Priority Bids Sent Over Serial Links to a Multi-Port Storage Device
Patent:
7,171,525 →
Application:
10/210,839 →
Cyclic phase signal generation from a single clock source using current phase interpolation
Patent:
6,380,783 →
Application:
09/688,536 →
Fully Differential Continuous-Time Current-Mode High Speed Cmos Comparator
Voltage Swing Detection Circuit for Hot Plug Event or Device Detection via a Differential Link
Patent:
7,009,827 →
Application:
10/270,882 →
Method and Apparatus for Connecting Serial Ata Storage Components
Patent:
6,843,674 →
Application:
10/162,046 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Patent:
7,131,004 →
Application:
09/945,278 →
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
Method and Apparatus for Encrypting Data Transmitted Over a Serial Link
System and Method for an Adaptive State Machine to Control Signal Filtering in a Serial Link
Patent:
7,218,737 →
Application:
10/224,995 →
Method and System for Encrypting and Decrypting Data Using an External Agent
Patent:
7,242,766 →
Application:
09/991,057 →
Method and System for Temporary Interruption of Video Data Transmission
Patent:
7,035,290 →
Application:
10/085,177 →
Method and System for Host Handling of Communications Errors
Method and System for Communicating Control Information via Out-of-Band Symbols
Method and System for Integrating Packet Type Information with Synchronization Symbols
Method and System for Nesting of Communications Packets
Method and System for Dc-Balancing at the Physical Layer
Patent:
6,771,192 →
Application:
10/045,600 →
Multisection Memory Bank System
Logic Gates Including Diode-Connected Metal-Oxide-Semiconductor Field-Effect Transistors (Mosfets) to Control Input Threshold Voltage Levels and Switching Transients of Output Logic Signals
Patent:
7,058,121 →
Application:
09/989,647 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Patent:
6,985,005 →
Application:
09/989,487 →
Differential Amplifiers Using Asymmetric Transfer Characteristics to Suppress Input Noise in Output Logic Signals
Transmitter and Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers to Suppress Noise
Continuous-Time, Low-Frequency-Gain/High-Frequency-Boosting Joint Adaptation Equalizer and Method
Patent:
6,819,166 →
Application:
10/403,477 →
Video/Graphics Text Mode Enhancement Method for Digitally Processed Data
Patent:
7,348,991 →
Application:
10/417,712 →
Detection of Video Windows and Graphics Windows
Patent:
6,873,341 →
Application:
10/287,976 →
Integrated Circuit Having Self Test Capability Using Message Digest and Method for Testing Integrated Circuit Having Message Digest Generation Circuitry
Patent:
7,539,304 →
Application:
10/298,722 →
Dynamically Biased Full-Swing Operation Amplifier for an Active Matrix Liquid Crystal Display Driver
Patent:
6,717,468 →
Application:
10/215,936 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,412,053 →
Application:
10/268,832 →
Cryptographic Device with Stored Key Data and Method for Using Stored Key Data to Perform an Authentication Exchange or Self Test
Patent:
7,797,536 →
Application:
11/950,088 →
Through-Board Pcb Edge Connector, System and Method
Patent:
6,814,583 →
Application:
10/244,152 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Patent:
8,064,508 →
Application:
10/247,675 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Cmos Transceiver with Dual Current Path Vco
Patent:
7,551,909 →
Application:
10/651,500 →
Combining a Clock Signal and a Data Signal
Data Sampling Method and Apparatus with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization
Patent:
7,409,031 →
Application:
10/642,259 →
Method and System for Encapsulation of Multiple Levels of Communication Protocol Functionality Within Line Codes
Patent:
7,187,307 →
Application:
10/459,989 →
Method and Circuit for Adaptive Equalization of Multiple Signals in Response to a Control Signal Generated from One of the Equalized Signals
Method and Apparatus for Encoding or Decoding Data in Accordance with an Nb/(N+1)B Block Code, and Method for Determining Such a Block Code
Patent:
6,747,580 →
Application:
10/459,992 →
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
Apparatus for Removably Securing Storage Components in an Enclosure
Reduced Dead-Cycle, Adaptive Phase Tracking Method and Apparatus
Patent:
7,236,553 →
Application:
10/763,905 →
Method and Apparatus for Run Length Limited Tmds-Like Encoding of Data
Patent:
6,897,793 →
Application:
10/835,301 →
Data Sampling Method and Apparatus Using Through-Transition Counts to Reject Worst Sampling Position
Patent:
7,991,096 →
Application:
10/842,231 →
Method and Circuit for Dc Measurement of Phase Uniformity of Multi-Phase Clocks
Patent:
7,031,858 →
Application:
10/439,446 →
Age Selection Switching Scheme for Data Traffic in a Crossbar Switch
Patent:
7,274,690 →
Application:
10/302,436 →
Preference Programmable First-One Detector and Quadrature Based Random Grant Generator
Patent:
7,505,422 →
Application:
10/645,786 →
Method for Multicast Service in a Crossbar Switch
Patent:
7,461,167 →
Application:
10/645,787 →
Content Addressable Merged Queue Architecture for Switching Data
Patent:
7,352,764 →
Application:
10/762,950 →
Method for Switching Data in a Crossbar Switch
Patent:
7,519,066 →
Application:
10/434,785 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Parallel Interface Bus to Communicate Video Data Encoded for Serial Data Links
Phase Lock Loop with Coarse Control Loop Having Frequency Lock Detector and Device Including Same
Patent:
7,102,446 →
Application:
11/056,995 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Current Mode Circuitry to Modulate a Common Mode Voltage
Test Clock Control Structures to Generate Configurable Test Clocks for Scan-Based Testing of Electronic Circuits Using Programmable Test Clock Controllers
Parameter Scanning for Signal Over-Sampling
Determining Oversampled Data to Be Included in Unit Intervals
Smart scalable storage switch architecture
Covert Channel for Conveying Supplemental Messages in a Protocol-Defined Link for a System of Storage Devices
Adaptive Bandwidth Phase Locked Loop with Feedforward Divider
Concurrent Code Checker and Hardware Efficient High-Speed I/O Having Built-in Self-Test and Debug Features
Inter-Port Communication in a Multi-Port Memory Device
Multi-Port Memory Device Having Variable Port Speeds
Shared Nonvolatile Memory Architecture
Scan-Based Testing of Devices Implementing a Test Clock Control Structure ("Tccs")
Signal Interleaving for Serial Clock and Data Recovery
Progressive Power Control of a Multi-Port Memory Device
Interface Test Circuitry and Methods
Ensuring Physical Locality of Entities Sharing Data
Circuitry to Prevent Peak Power Problems During Scan Shift
Power-Saving Clocking Technique
Method of Context Adaptive Binary Arithmetic Coding and Coding Apparatus Using the Same
Patent:
7,365,659 →
Application:
11/567,514 →
Operation of Media Interface to Provide Bidirectional Communications
Delivering on Screen Display Data to Existing Display Devices
On Screen Displays Associated with Remote Video Source Devices
Bandwidth Reservation for Data Flows in Interconnection Networks
Data Stream Control for Network Devices
Automated Service Discovery and Dynamic Connection Management
Network Repository for Metadata
Packet Level Prioritization in Interconnection Networks
Synchronizing Related Data Streams in Interconnection Networks
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Method, Apparatus, and System for Port Multiplier Enhancement
Semiconductor Memory Device
Related Assignments
(11)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 12, 2015
From: NORTHCUTT, J. DUANE; HANKO, JAMES G.; SCHMIDT, BRIAN K.
To: SILICON IMAGE, INC.
Reel/Frame 036310/0471 →
Merger
Aug 12, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036310/0482 →
Merger
Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
Release of Security Interest
Oct 28, 2015
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036905/0327 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Security Interest
Jul 18, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049795/0481 →
Assignment of Assignor's Interest
Sep 9, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: KONINKLIJKE PHILIPS N.V.
Reel/Frame 050314/0434 →
Release of Security Interest
Nov 10, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 058067/0896 →
Assignment of Assignor's Interest
Dec 16, 2021
From: LATTICE SEMICONDUCTOR CORPORATION
To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
Reel/Frame 058979/0440 →
Assignment of Assignor's Interest
Jul 4, 2024
From: KONINKLIJKE PHILIPS N.V.
To: GENERAL VIDEO, LLC
Reel/Frame 067912/0351 →