Adaptive bandwidth phase locked loop with feedforward divider

1. A chip comprising:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop (PLL) control circuitry to select the first and second division factors while considering an optimal voltage value;

wherein the PLL control circuitry selects the first and second division factors in response to the first and second output clock signals and the first and second feedforward voltage signal inputs into the first and second VCOs.

2. The chip of claim 1 , wherein the first division factor is typically different than the second division factor.

3. A chip comprising:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop (PLL) control circuitry to select the first and second division factors;

wherein the PLL control circuitry selects the first and second division factors while considering an optimal value.

4. The chip of claim 1 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

5. A chip comprising:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop (PLL) control circuitry to select the first and second division factors while considering an optimal voltage value;

wherein the first division factor is equal to 2 raised to an integer power and the second first division factor is equal to 2 raised to an integer power, and wherein the integer for the first division factor is typically different than the integer for the second division factor.

6. The chip of claim 5 , wherein the integers of the first sub-PLL are even integers and the integers of the second sub-PLL are odd integers.

7. The chip of claim 1 , wherein while one sub-PLL is provide the output, PLL control circuitry may change the division factor for the other sub-PLL.

8. A chip comprising:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop (PLL) control circuitry to select the first and second division factors while considering an optimal voltage value;

wherein the first and second sub-PLLs include:

first and second phase frequency detectors; and

first and second feedback divider circuits to divide the frequency of divided first and second VCO output signals and provide them to the first and second phase frequency detectors.

9. A method comprising:

providing first and second voltage controlled oscillators (VCOs) of first and second sub phase lock loops (sub-PLLs) with voltage control signals;

outputting first and second VCO output signals and first and second feedforward divider circuits from the first and second VCOs;

dividing first and second frequencies of the first and second VCO output signals by first and second division factors; and

selecting the first and second division factors while considering an optimal voltage value;

wherein the PLL control circuitry selects the first and second division factors in response to the first and second output clock signals and the first and second feedforward feedforward voltage signal inputs into the first and second VCOs.

10. The method of claim 9 , further comprising selecting the output of the first or the second sub-PLLs as a PLL output signal.

11. A method comprising:

providing first and second voltage controlled oscillators (VCOs) of first and second sub phase lock loops (sub-PLLs) with voltage control signals;

outputting first and second VCO output signals and first and second feedforward divider circuits from the first and second VCOs;

dividing first and second frequencies of the first and second VCO output signals by first and second division factors; and

selecting the first and second division factors;

wherein PLL control circuitry selects the first and second division factors while considering an optimal voltage value.

12. The method of claim 11 , wherein the first division factor is typically different than the second division factor.

13. A chip comprising:

at least one conductor carrying an input clock signal;

a dual phase locked loop (dual-PLL) including:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop control circuitry to select the first and second division factors while considering an optimal voltage value;

wherein the PLL control circuitry selects the first and second division factors in response to the first and second output clock signals and the first and second feedforward voltage signal inputs into the first and second VCOs.

14. The chip of claim 13 , wherein the first division factor is typically different than the second division factor.

15. A chip comprising:

at least one conductor carrying an input clock signal;

a dual phase locked loop (dual-PLL) including:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop control circuitry to select the first and second division factors;

wherein the PLL control circuitry selects the first and second division factors while considering an optimal voltage value.

16. The chip of claim 13 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

17. A chip comprising:

at least one conductor carrying an input clock signal;

a dual phase locked loop (dual-PLL) including:

first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors; and

phase locked loop control circuitry to select the first and second division factors while considering an optimal voltage value;

wherein the first division factor is equal to 2 raised to an integer power and the second first division factor is equal to 2 raised to an integer power, and wherein the integer for the first division factor is typically different than the integer for the second division factor.

18. The chip of claim 3 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

19. The chip of claim 5 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

20. The chip of claim 8 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

21. The chip of claim 3 , wherein while one sub-PLL is provided to an ouput, PLL control circuitry may change the division factor for the other sub-PLL.

22. The chip of claim 5 , wherein while one sub-PLL is provided to an output, PLL control circuitry may change the division factor for the other sub-PLL.

23. The chip of claim 8 , wherein while one sub-PLL is provided to an output, PLL control circuitry may change the division factor for the other sub-PLL.

24. The chip of claim 15 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.

25. The chip of claim 17 , further comprising output signal selection circuitry to select either the divided first and second VCO output signals under the control of the phase locked loop control circuitry.