IP Library Assignment 036905/0327
Patent Assignment
Reel/Frame 036905/0327

Release of Security Interest

Recorded: 2015-10-28 Pages: 7
Assignor
JEFFERIES FINANCE LLC
Executed: 2015-10-28
Assignee
LATTICE SEMICONDUCTOR CORPORATION
111 SW 5TH AVENUE, 7TH FLOOR, PORTLAND, OREGON, 97204
Covered Properties (34)
Dual Loop Delay-Locked Loop
Patent: 5,969,552 →
Application: 09/007,707 →
Methods and Apparatus for Variable Length Sdram Transfers
Patent: 6,219,747 →
Application: 09/226,776 →
Methods and Apparatus for Data Bus Arbitration
Patent: 6,393,505 →
Application: 09/227,502 →
Wide frequency-range delay-locked loop circuit
Patent: 6,326,826 →
Application: 09/574,571 →
Methods and Apparatus for Variable Length Sdram Transfers
Patent: 6,385,692 →
Application: 09/805,588 →
Publication: US 2002/0007435
Method and System for Nesting of Communications Packets
Patent: 7,154,905 →
Application: 10/035,911 →
Publication: US 2004/0004975
Method and System for Host Handling of Communications Errors
Patent: 6,976,201 →
Application: 10/036,794 →
Publication: US 2002/0157054
Memory Architecture with Multiple Serial Communications Ports
Patent: 7,257,129 →
Application: 10/045,297 →
Publication: US 2002/0191475
Method and System for Transition-Controlled Selective Block Inversion Communications
Patent: 7,039,121 →
Application: 10/045,393 →
Publication: US 2003/0210162
Method and System for Dc-Balancing at the Physical Layer
Patent: 6,771,192 →
Application: 10/045,600 →
Multisection Memory Bank System
Patent: 7,340,558 →
Application: 10/045,601 →
Publication: US 2003/0208655
Method and System for Integrating Packet Type Information with Synchronization Symbols
Patent: 7,746,798 →
Application: 10/045,625 →
Publication: US 2002/0172200
Method and System for Communicating Control Information via Out-of-Band Symbols
Patent: 7,113,507 →
Application: 10/053,461 →
Publication: US 2003/0227947
Data Synchronization Across an Asynchronous Boundary Using, for Example, Multi-Phase Clocks
Patent: 7,231,009 →
Application: 10/371,220 →
Publication: US 2004/0161067
Shared Nonvolatile Memory Architecture
Patent: 7,831,778 →
Application: 11/690,629 →
Publication: US 2007/0233938
Progressive Power Control of a Multi-Port Memory Device
Patent: 7,908,501 →
Application: 11/690,642 →
Publication: US 2008/0235528
Power-Saving Clocking Technique
Patent: 7,849,339 →
Application: 11/690,659 →
Publication: US 2008/0235526
Multi-Port Memory Device Having Variable Port Speeds
Patent: 7,639,561 →
Application: 11/694,813 →
Publication: US 2007/0245094
Inter-Port Communication in a Multi-Port Memory Device
Patent: 7,949,863 →
Application: 11/694,819 →
Publication: US 2007/0234021
Communications Architecture for Transmission of Data Between Memory Bank Caches and Ports
Patent: 7,903,684 →
Application: 11/828,286 →
Publication: US 2008/0126824
Signal Interleaving for Serial Clock and Data Recovery
Patent: 8,160,192 →
Application: 11/861,175 →
Publication: US 2008/0075222
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Patent: 8,001,334 →
Application: 11/952,052 →
Publication: US 2009/0150621
Method, Apparatus, and System for Automatic Data Aligner for Multiple Serial Receivers
Patent: 8,036,248 →
Application: 12/260,970 →
Publication: US 2010/0103929
Coding System for Memory Systems Employing High-Speed Serial Links
Patent: 7,777,652 →
Application: 12/260,972 →
Publication: US 2010/0102999
Computer Memory Test Structure
Patent: 8,386,867 →
Application: 12/497,391 →
Publication: US 2011/0004793
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Patent: 8,543,873 →
Application: 12/683,365 →
Publication: US 2011/0167308
Hybrid Interface for Serial and Parallel Communication
Patent: 8,510,487 →
Application: 12/704,417 →
Publication: US 2011/0196997
17B/20B Coding System
Patent: 7,978,099 →
Application: 12/847,416 →
Publication: US 2010/0295711
Configurable Multi-Dimensional Driver and Receiver
Patent: 8,760,188 →
Application: 13/174,616 →
Publication: US 2013/0002290
Computer Memory Test Structure
Patent: 8,667,354 →
Application: 13/776,508 →
Publication: US 2013/0173974
Hybrid Interface for Serial and Parallel Communication
Patent: 8,751,709 →
Application: 13/934,147 →
Publication: US 2013/0290581
Multi-Site Testing of Computer Memory Devices and Serial Io Ports
Patent: 8,839,058 →
Application: 14/035,795 →
Publication: US 2014/0026006
Computer Memory Test Structure
Patent: 8,924,805 →
Application: 14/145,751 →
Publication: US 2014/0115414
Configurable Multi-Dimensional Driver and Receiver
Patent: 9,281,969 →
Application: 14/300,166 →
Publication: US 2014/0286388
Related Assignments (11)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 26, 2015
From: SHIN, YESHIK
To: SILICON IMAGE, INC.
Reel/Frame 035044/0148 →
Assignment of Assignor's Interest Feb 26, 2015
From: SHIN, YESHIK
To: SILICON IMAGE, INC.
Reel/Frame 035044/0324 →
Assignment of Assignor's Interest Feb 26, 2015
From: SHIN, YESHIK
To: SILICON IMAGE, INC.
Reel/Frame 035044/0457 →
Security Interest Mar 17, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035220/0226 →
Security Interest Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0147 →
Merger Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
Security Interest May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Security Interest Jul 18, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049795/0481 →
Release of Security Interest Nov 10, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 058067/0896 →
Assignment of Assignor's Interest Dec 16, 2021
From: LATTICE SEMICONDUCTOR CORPORATION
To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
Reel/Frame 058979/0440 →