Granted Patent B2

US 9,281,969 · App. 14/300,166 · Granted Mar 8, 2016

Abstract

Claims (44)

1. A reflection cancellation apparatus comprising:

a predriver including a plurality of elements, each of the plurality of elements to receive one of a plurality of clock signals and to provide a data sample delayed by a time determined by the respective clock signal;

a plurality of circuit units each coupled to receive a data signal sample from a respective one of the plurality of elements of the predriver, and each of the plurality of circuit units coupled at an output node to output an output signal to an communication channel; and

a time adjustment unit to generate the plurality of clock signals and to adjust timing of the plurality of clock signals to at least partially cancels noise in the output signal caused by a signal reflection from the communication channel, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel.

2. The reflection cancellation apparatus of claim 1 , wherein each of the plurality of circuit units comprises:

a first transistor, a first terminal of the first transistor being coupled with a supply voltage;

a first resistor, a first end of the first resistor being coupled with a second terminal of the first transistor and a second end of the first resistor being coupled with the output node;

a second transistor, a first terminal of the second transistor being coupled with ground; and

a second resistor, a first end of the second resistor being coupled with a second terminal of the second transistor and a second end of the second resistor being coupled with the output node.

3. The reflection cancellation apparatus of claim 1 , wherein the time adjustment unit includes:

a delayed lock loop element to receive a clock signal and generate a plurality of phase-adjusted clock signals; and

a phase interpolator element coupled with the delayed lock loop element to receive the plurality of phase-adjusted clock signals, the phase interpolator element to receive data signal phase codes from calibration logic and generate the plurality of clocks signals based on the plurality of phase-adjusted clocks signals and the phase codes.

4. The reflection cancellation apparatus of claim 3 , further comprising:

calibration logic to generate the phase codes based on feedback from a receiver.

5. A method for canceling a reflection from a communication channel coupled to a driver circuit, the method comprising:

generating a plurality of clock signals, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel;

delaying a plurality data samples by different delay times, the different delay times each corresponding to one of the plurality of clock signals;

generating an output signal based on the plurality of delayed samples each having different delay times; and

adjusting the different delay times applied to the plurality of data samples such that a signal reflection from transmitting the output signal over the channel is at least partially canceled.

6. The method of claim 5 , wherein the generating the plurality of clock signals comprises:

receiving a clock signal and generate a plurality of phase-adjusted clock signals; and

receiving data signal phase codes from calibration logic; and

generating the plurality of clocks signals based on the plurality of phase-adjusted clocks signals and the data signal phase codes.

7. The method of claim 6 , further comprising:

generating the phase codes based on feedback from a receiver.

8. A communication system comprising:

a communication channel;

a first device coupled with the communication channel, the first device including a driver apparatus to drive data signals on the communication channel, the driver apparatus comprising:

a predriver including a plurality of elements, each of the plurality of elements to receive one of a plurality of clock signals and to provide a data sample delayed by a time determined by the respective clock signal;

a plurality of circuit units each coupled to receive a data signal sample from a respective one of the plurality of elements of the predriver, and each of the plurality of circuit units coupled at an output node to output an output signal to the communication channel; and

a time adjustment unit to generate the plurality of clock signals and to adjust timing of the plurality of clock signals to at least partially cancels noise in the output signal caused by a signal reflection from the communication channel, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel;

a second device coupled with the communication channel, the second device including a receiver to receive the output signal from the communication channel.

9. The communication system of claim 8 , wherein each of the plurality of circuit units comprises:

a first transistor, a first terminal of the first transistor being coupled with a supply voltage;

a first resistor, a first end of the first resistor being coupled with a second terminal of the first transistor and a second end of the first resistor being coupled with the output node;

a second transistor, a first terminal of the second transistor being coupled with ground; and

a second resistor, a first end of the second resistor being coupled with a second terminal of the second transistor and a second end of the second resistor being coupled with the output node.

10. The communication system of claim 8 , wherein the time adjustment unit includes:

a delayed lock loop element to receive a clock signal and generate a plurality of phase-adjusted clock signals; and

a phase interpolator element coupled with the delayed lock loop element to receive the plurality of phase-adjusted clock signals, the phase interpolator element to receive data signal phase codes from calibration logic and generate the plurality of clocks signals based on the plurality of phase-adjusted clocks signals and the phase codes.

11. The communication system of claim 10 , wherein the driver circuit further comprises:

calibration logic to generate the phase codes based on feedback from the receiver.

12. The communication system of claim 8 , wherein the second device further comprises:

a reference voltage selection block coupled to an receive an output of the receiver and to provide one of a plurality of reference voltages as a second input to the receiver.

Assignments (6)