Patent Assignment
Reel/Frame 035223/0387
Security Interest
Recorded: 2015-03-18
Pages: 82
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(86)
Digital Video Interface with Bi-Directional Half-Duplex Clock Channel Used as Auxiliary Data Channel
Adaptive Equalizer for Use with Clock and Data Recovery Circuit of Serial Communication Link
Bi-Directional Digital Interface for Video and Audio (Diva)
Passive Equalizer with Negative Impedance to Increase a Gain
Power Delivery Over Digital Interaction Interface for Video and Audio (Diiva)
Enhanced Wireless Data Rates Using Multiple Beams
Patent:
8,588,193 →
Application:
12/699,758 →
Enhanced Wireless Data Rates Using Multiple Beams
Patent:
8,457,026 →
Application:
12/699,781 →
Apparatus, System, and Method for a Compact Symmetrical Transition Structure for Radio Frequency Applications
Identification and Handling of Data Streams Using Coded Preambles
Mechanism for Facilitating Cost-Efficient and Low-Latency Encoding of Video Streams
Application:
13/460,393 →
Publication:
US 2013/0287100
MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA)
Application:
13/521,739 →
Publication:
US 2013/0191570
Video Management and Control in Home Multimedia Network
Test Solution for Ring Oscillators
Combining Video and Audio Streams Utilizing Pixel Repetition Bandwidth
Interfacing Between Integrated Circuits with Asymmetric Voltage Swing
Methods and Apparatuses to Provide an Electro-Optical Alignment
Mechanism for Facilitating Dynamic Timestamp-Less Clock Generation for Transmitting Media Streams Over Shared Channels
Method and Apparatus for Reducing Digital Video Image Data
Application:
13/738,768 →
Publication:
US 2014/0152891
Configurable Single-Ended Driver
Transmitting Multiple Differential Signals Over a Reduced Number of Physical Channels
Apparatus, System and Method for Providing Clock and Data Signaling
Integrated Connector/Flex Cable
Auxiliary Data Encoding in Video Data
Application:
13/787,664 →
Publication:
US 2014/0204994
Mechanism for Facilitating Synchronization of Audio and Video Between Multiple Media Devices
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Integration of Signal Sampling Within Transistor Amplifier Stage
Full-Frame Buffer to Improve Video Performance in Low-Latency Video Communication Systems
Electronic Alignment of Optical Signals
Application:
13/844,152 →
Publication:
US 2014/0193165
Method, Apparatus and System for Communicating Sideband Data with Non-Compressed Video
Patent:
8,786,776 →
Application:
13/891,842 →
Multiple Protocol Tunneling Using Time Division Operations
Integrated Mobile Desktop
Elements to Counter Transmitter Circuit Performance Limitations
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Compensation Scheme for Mhl Common Mode Clock Swing
Line Driver with Separate Pre-Driver for Feed-Through Capacitance
Driving Data of Multiple Protocols Through a Single Set of Pins
Formatting Audio-Video Information Compliant with First Transmission Format to Second Transmission Format in Integrated Circuit for Offloading Physical Layer Logic for First Transmission Format to Separate Integrated Circuit
Messaging to Provide Data Link Integrity
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Mechanism for Facilitating Dynamic Counter Synchronization and Packetization in High-Definition Multimedia Interface and Mobile High-Definition Link
Apparatus, System and Method for Providing Switching with a T-Coil Circuit
Apparatus, Method and System for Asymmetric, Full-Duplex Communication
Power Delivery Over Digital Interaction Interface for Video and Audio (DiiVA)
Video Frame Synchronization
Application:
14/184,647 →
Publication:
US 2014/0168514
Test Solution for a Random Number Generator
Method and Apparatus for Implementing Wide Data Range and Wide Common-Mode Receivers
Communication of Multimedia Data Streams over Multiple Communication Lanes
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Error Detection and Mitigation in Video Channels
Application:
14/275,692 →
Publication:
US 2015/0326884
Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding
Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures
Transmitting Apparatus with Source Termination
Configurable Multi-Dimensional Driver and Receiver
Cable with Circuitry for Communicating Performance Information
Phase-Modulated On-Off Keying for Millimeter Wave Spectrum Control
Patent:
9,178,735 →
Application:
14/339,393 →
Caching of Capabilities Information of Counterpart Device for Efficient Handshaking Operation
Charge Pump Calibration for Dual-Path Phase-Locked Loop
Linear Regulator with Improved Power Supply Ripple Rejection
Techniques for Fractional-N Phase Locked Loops
Frequency Response Compensation in a Digital to Analog Converter
Radio Frequency Interference Reduction In Multimedia Interfaces
System and Method for Transcoding Data
Compressed Video Transfer over a Multimedia Link
Application:
14/470,613 →
Publication:
US 2015/0256842
Compressed Blanking Period Transfer Over a Multimedia Link
Arbitration Signaling Within a Multimedia High Definition Link (Mhl 3) Device
Phase Relationship Control for Control Channel of a Multimedia Communication Link
Retry Disparity for Control Channel of a Multimedia Communication Link
Enhanced Communication Link Using Synchronization Signal as Link Command
Application:
14/483,013 →
Publication:
US 2016/0072601
Electrical Connector with Optical Channel
Application:
14/502,928 →
Publication:
US 2016/0091669
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Determination of Physical Connectivity Status of Devices Based on Electrical Measurement
Electrical Duplex to Optical Conversion
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Displaying Multiple Videos on Sink Device Using Display Information of Source Device
Low Power Operations in a Wireless Tunneling Transceiver
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Pre-Processor and Post-Processor for Compression of 4:2:0 Encoded Video Streams with Video Compression Codecs Embedded within an Audio/Video Standard
Application:
61/943,267 →
Reversible Connector
Application:
61/947,704 →
Compressed Video Transfer Over Hdmi and Mhl
Application:
61/949,901 →
Error Correction for Transmission of Compressed Video Data over Standards-Defined Coded Audio/Video Links
Application:
61/973,837 →
(MHL) Connector Cable Detect, Cable Orientation Detect and/or Lane Re-Mapping
Application:
61/975,517 →
MHL3 Router without HDCP2.2 Decryption and Encryption Operation
Application:
61/979,477 →
TDD over 5-Pin Interface
Application:
61/979,483 →
System for Dynamic Capabilities, Status, and Metadata Exchange
Application:
61/989,409 →
Secure Control Communication Between an Application Processor and a Transmitter
Application:
62/061,630 →
Metadata Transfer for HDMI/MHL
Application:
62/075,554 →
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 2, 2012
From: YANG, WOOSEUNG; YI, JU HWAN; KIM, YOUNG IL; CHOI, HOON
To: SILICON IMAGE, INC.
Reel/Frame 028142/0007 →
Assignment of Assignor's Interest
Sep 12, 2012
From: ALTMANN, WILLIAM CONRAD
To: SILICON IMAGE, INC.
Reel/Frame 028947/0363 →
Assignment of Assignor's Interest
Sep 18, 2012
From: GONDI, SRIKANTH; ISAAC, ROGER
To: SILICON IMAGE, INC.
Reel/Frame 028981/0833 →
Assignment of Assignor's Interest
Nov 7, 2012
From: KIM, KIHONG
To: SILICON IMAGE, INC.
Reel/Frame 029259/0653 →
Assignment of Assignor's Interest
Nov 13, 2012
From: SUL, CHINSONG; KWON, HYUKYONG; NG, ANDY
To: SILICON IMAGE, INC.
Reel/Frame 029290/0052 →
Nunc Pro Tunc Assignment
Dec 12, 2012
From: SYNERCHIP CO., LTD.
To: SILICON IMAGE, INC.
Reel/Frame 029451/0939 →
Assignment of Assignor's Interest
Jan 8, 2013
From: YI, JU HWAN; KIM, YOUNG IL; BAE, YOUNG DON
To: SILICON IMAGE, INC.
Reel/Frame 029591/0300 →
Assignment of Assignor's Interest
Oct 1, 2013
From: SYNERCHIP CO., LTD.
To: SILICON IMAGE, INC.
Reel/Frame 031322/0430 →
Assignment of Assignor's Interest
Oct 1, 2013
From: SYNERCHIP TECHNOLOGY CO., LTD.
To: SYNERCHIP CO., LTD.
Reel/Frame 031322/0409 →
Corrective Assignment to Correct the Assignee Names and Addresses, Date of Execution, Conveyance Type, and Supporting Legal Documentation Previously Recorded on Reel 029815 Frame 0156. Assignor(S) Hereby Confirms the Assignees Are Synerchip Co., Ltd. and Silicon Image, Inc.; Date of Execution Is 12/31/2013; and Conveyance Type Is Assignment.
Jan 17, 2014
From: SYNERCHIP CO., LTD.
To: SYNERCHIP CO., LTD.; SILICON IMAGE, INC.
Reel/Frame 032087/0935 →
Merger
Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
Release of Security Interest
Mar 7, 2017
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 041905/0860 →
Assignment of Assignor's Interest
Mar 7, 2017
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 041905/0814 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Security Interest
Jul 18, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049795/0481 →
Merger
Oct 25, 2021
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 057902/0098 →
Release of Security Interest
Nov 10, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 058067/0896 →
Assignment of Assignor's Interest
Dec 16, 2021
From: LATTICE SEMICONDUCTOR CORPORATION
To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
Reel/Frame 058979/0440 →