Arbitration signaling within a multimedia high definition link (MHL 3) device

1. A device for interfacing with a peer device via a multimedia communication link having a multimedia bus and a control bus in full duplex or in half duplex, the device comprising:

a half-duplex translation layer circuit to interface with software of the device in half duplex, the half-duplex translation layer circuit to exchange control data with the software and to communicatively couple to a half-duplex link layer circuit or a full duplex link layer circuit;

the full-duplex link layer circuit to communicate the control data with the peer device over the control bus in full duplex;

the half-duplex link layer circuit to communicate the control data with the peer device over the control bus in half duplex;

an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow of the control data between the half-duplex translation layer circuit and the full-duplex link layer circuit by regulating transmission requests and receive requests; and

a multiplexing circuit communicatively coupled to the half-duplex translation layer circuit and configured to selectively connect the half-duplex link layer circuit or connect the full-duplex link layer circuit to the half-duplex translation layer circuit based on capabilities of the peer device.

2. The device of claim 1 , wherein:

the arbitration circuit receives a transmission request from the half-duplex translation layer circuit and a receive request from the full-duplex link layer circuit; and

responsive to the transmission request and the receive request, the arbitration circuit grants the receive request and holds the transmission request until a receive transaction associated with the receive request is completed.

3. The device of claim 1 , wherein:

the arbitration circuit receives a receive request while in a data transmission state; and

responsive to receiving the receive request while in the data transmission state, the arbitration circuit aborts the data transmission state and grants the receive request.

4. The device of claim 1 , wherein, while the arbitration circuit is in a data transmission state, if the arbitration circuit fails to receive a transmission grant from the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

5. The device of claim 1 , wherein, while the arbitration circuit is in a data receiving state, if the arbitration circuit fails to receive a transmission grant from the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

6. The device of claim 1 , wherein, while the arbitration circuit is in a data transmission state, if the arbitration circuit fails to receive a handshake signal from a peer device via the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

7. The device of claim 1 , wherein the arbitration circuit comprises a state machine that controls flow of data between the half-duplex translation layer circuit and the full-duplex link layer circuit.

8. The device of claim 1 , wherein the half-duplex translation layer circuit is configured to enable a single selected logical channel, of a plurality of logical channels, to access the control bus at a time.

9. The device of claim 1 , wherein the full-duplex link layer circuit is configured to specify schemes for framing data received from the half-duplex translation layer circuit into link layer packets.

10. The device of claim 1 , wherein the full-duplex link layer circuit comprises a time division multiplexer circuit to control timing and synchronization for packets transmitted over the control bus.

11. The device of claim 1 , wherein the arbitration circuit controls data flow between the half-duplex translation layer circuit and the full-duplex link layer circuit by administering interface and signaling rules for:

transmitting data packets from the half-duplex translation layer circuit to the full-duplex link layer circuit;

receiving data packets via the full-duplex link layer at the half-duplex translation layer; and

resolving conflict arising due to bidirectional data flow at the arbitration circuit.

12. A non-transitory computer-readable medium storing a representation of a device for interfacing with a peer device via a multimedia communication link having a multimedia bus and a control bus in full duplex or in half duplex, the device comprising:

a half-duplex translation layer circuit to interface with software of the device in half duplex, the half-duplex translation layer circuit to exchange control data with the software and to communicatively couple to a half-duplex link layer circuit or a full duplex link layer circuit;

the full-duplex link layer circuit to communicate the control data with the peer device over the control bus in full duplex;

the half-duplex link layer circuit to communicate the control data with the peer device over the control bus in half duplex;

an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow of the control data between the half-duplex translation layer circuit and the full-duplex link layer circuit by regulating transmission requests and receive requests; and

a multiplexing circuit communicatively coupled to the half-duplex translation layer circuit and configured to selectively connect the half-duplex link layer circuit or connect the full-duplex link layer circuit to the half-duplex translation layer circuit based on capabilities of the peer device.

13. The non-transitory computer-readable medium of claim 12 , wherein:

the arbitration circuit receives a transmission request from the half-duplex translation layer circuit and a receive request from the full-duplex link layer circuit; and

responsive to the transmission request and the receive request, the arbitration circuit grants the receive request and holds the transmission request until a receive transaction associated with the receive request is completed.

14. The non-transitory computer-readable medium of claim 12 , wherein:

the arbitration circuit receives a receive request while in a data transmission state; and

responsive to receiving the receive request while in the data transmission state, the arbitration circuit aborts the data transmission state and grants the receive request.

15. The non-transitory computer-readable medium of claim 12 , wherein while the arbitration circuit is in a data transmission state, if the arbitration circuit fails to receive a transmission grant from the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

16. The non-transitory computer-readable medium of claim 12 , wherein, while the arbitration circuit is in a data receiving state, if the arbitration circuit fails to receive a transmission grant from the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

17. The non-transitory computer-readable medium of claim 12 , wherein, while the arbitration circuit is in a data transmission state, if the arbitration circuit fails to receive a handshake signal from a peer device via the full-duplex link layer circuit within a pre-determined period of time, the arbitration circuit generates a signal causing a reset of protocol states of the half-duplex translation layer circuit or of the full-duplex link layer circuit.

18. The non-transitory computer-readable medium of claim 12 , wherein the arbitration circuit comprises a state machine that controls flow of data between the half-duplex translation layer circuit and the full-duplex link layer circuit.

19. The device of claim 1 , further comprising:

a first port to interface with the multimedia bus for transmission of video data over the multimedia bus to the peer device; and

a second port to interface with the control bus for transmission of the control data over the control bus to the peer device.

20. The device of claim 1 , wherein selectively connecting the half-duplex link layer circuit or connecting the full-duplex link layer circuit to the half-duplex translation layer circuit based on capabilities of the peer device comprises:

connecting the half-duplex link layer circuit to the half-duplex translation layer circuit responsive to the peer device being configured to operate in half-duplex; and

connecting the full-duplex link layer circuit to the half-duplex translation layer circuit responsive to the peer device being configured to operate in full-duplex.