Frequency response compensation in a digital to analog converter

1. An n-bit digital to analog converter comprising:

a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream corresponding to bit values of the input bit stream at a time;

a first delay circuit coupled to the receiving circuit to receive the first bit signal stream, the delay circuit configured to generate a second bit signal stream representing a version of the first bit signal stream delayed by a first period of time;

a first current generation circuit coupled to the receiving circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current to a first output responsive to receiving the first bit signal stream, the first current corresponding to the first bit signal stream; and

a second current generation circuit coupled to the delay circuit to receive the second bit signal stream, the second current generation circuit configured to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

2. The n-bit digital to analog converter of claim 1 , wherein the waveform of the second current lags the waveform of the first current by the first period of time.

3. The n-bit digital to analog converter of claim 1 , wherein:

the receiving circuit comprises a first set of n memory elements, each memory element of the first set configured to receive and store a bit value in one of n sub-streams of the input bit stream; and

the first delay circuit comprises a second set of n memory elements, each memory element of the second set coupled to a corresponding memory element of the first set to receive and store a bit value in one of n sub-streams of the first bit signal stream.

4. The n-bit digital to analog converter of claim 3 , wherein the first current generation circuit comprises a first set of n current sources and a first set of n switches, each current source of the first set of current sources coupled to the first output via a corresponding switch of the first set of switches, the corresponding switch turned on or off responsive to the bit value in one of n sub-streams of the first bit signal stream.

5. The n-bit digital to analog converter of claim 3 , wherein the second current generation circuit comprises a second set of n current sources and a second set of n switches, each current source of the second set of current sources coupled to the first output via a corresponding switch of the second set of switches, the corresponding switch turned on or off responsive to the bit value in one of n sub-streams of the second bit signal.

6. The n-bit digital to analog converter of claim 1 , further comprising:

one or more additional delay circuits coupled to the first delay circuit and configured to generate a third bit signal stream representing a version of the first bit signal stream delayed relative to the input bit stream by a second period of time that is greater than the first period of time; and

one or more corresponding additional current generation circuits coupled to the one or more additional delay circuits to receive the third bit signal stream and to provide a third current to the first output responsive to receiving the third bit signal stream, a waveform of the third current scaled relative to a waveform of the first current.

7. The n-bit digital to analog converter of claim 1 , further comprising a second output to receive a third current from the first current generation circuit and a fourth current from the second current generation circuit, a current at the second output in conjunction with a current at the first output forming a differential signal.

8. The n-bit digital to analog converter of claim 1 , wherein the waveform of the second current is up-scaled relative to the waveform of the first current.

9. The n-bit digital to analog converter of claim 1 , wherein the waveform of the second current is down-scaled relative to the waveform of the first current.

10. A method of operating an n-bit digital to analog converter, the method comprising:

receiving an input bit stream;

generating a first bit signal stream of the input bit stream corresponding to bit values of the input bit stream at a time;

generating a second bit signal stream representing a version of the first bit signal stream delayed by a first period of time;

providing first current to a first output based on the first bit signal stream, the first current corresponding to the first bit signal stream; and

providing second current to the first output based on the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

11. The method of claim 10 , further comprising:

generating a third bit signal stream representing a version of the first bit signal stream delayed relative to the input bit stream by a second period of time that is greater than the first period of time; and

providing a third current to the first output responsive to receiving the third bit signal stream, a waveform of the third current scaled relative to a waveform of the first current.

12. The method of claim 10 , further comprising:

providing a third current to a second output responsive to a representation of the first bit signal stream;

providing a fourth current to the second output responsive to a representation of the second bit signal stream; and

generating a differential signal based on a current at the second output in conjunction with a current at the first output.

13. A non-transitory computer readable medium storing a representation of an n-bit digital to analog converter, the n-bit digital to analog converter comprising:

a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream corresponding to bit values of the input bit stream at a time;

a first delay circuit coupled to the receiving circuit to receive the first bit signal stream, the delay circuit configured to generate a second bit signal stream representing a version of the first bit signal stream delayed by a first period of time;

a first current generation circuit coupled to the receiving circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current to a first output responsive to receiving the first bit signal stream, the first current corresponding to the first bit signal stream; and

a second current generation circuit coupled to the delay circuit to receive the second bit signal stream, the second current generation circuit configured to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

14. The non-transitory computer readable medium of claim 13 , wherein the waveform of the second current lags the waveform of the first current by the first period of time.

15. The non-transitory computer readable medium of claim 13 , wherein:

the receiving circuit comprises a first set of n memory elements, each memory element of the first set configured to receive and store a bit value in one of n sub-streams of the input bit stream; and

the first delay circuit comprises a second set of n memory elements, each memory element of the second set coupled to a corresponding memory element of the first set to receive and store a bit value in one of n sub-streams of the first bit signal stream.

16. The non-transitory computer readable medium of claim 15 , wherein the first current generation circuit comprises a first set of n current sources and a first set of n switches, each current source of the first set of current sources coupled to the first output via a corresponding switch of the first set of switches, the corresponding switch turned on or off responsive to the bit value in one of n sub-streams of the first bit signal stream.

17. The non-transitory computer readable medium of claim 15 , wherein the second current generation circuit comprises a second set of n current sources and a second set of n switches, each current source of the second set of current sources coupled to the first output via a corresponding switch of the second set of switches, the corresponding switch turned on or off responsive to the bit value in one of n sub-streams of the second bit signal.

18. The non-transitory computer readable medium of claim 13 , further comprising:

one or more additional delay circuits coupled to the first delay circuit and configured to generate a third bit signal stream representing a version of the first bit signal stream delayed relative to the input bit stream by a second period of time that is greater than the first period of time; and

one or more corresponding additional current generation circuits coupled to the one or more additional delay circuits to receive the third bit signal stream and to provide a third current to the first output responsive to receiving the third bit signal stream, a waveform of the third current scaled relative to a waveform of the first current.

19. The non-transitory computer readable medium of claim 13 , further comprising a second output to receive a third current from the first current generation circuit and a fourth current from the second current generation circuit, a current at the second output in conjunction with a current at the first output forming a differential signal.

20. The non-transitory computer readable medium of claim 13 , wherein the waveform of the second current is up-scaled or down-scaled relative to the waveform of the first current.