Multi-site testing of computer memory devices and serial IO ports

1. A memory testing apparatus comprising:

an input to receive data from one or more memory devices of a plurality of memory devices, each memory device of the plurality of memory devices having:

a differential serializer output including a first serializer node and a second serializer node, and

a differential deserializer input including a first deserializer node and a second deserializer node,

wherein the first serializer node of a first memory device is coupled to the first deserializer node of a second memory device,

the second serializer node of the first memory device is coupled to the first deserializer node of the first memory device,

the first serializer node of the second memory device is coupled to the second deserializer node of the second memory device, and

the second serializer node of the second memory device is coupled to the second deserializer node of the first memory device; and

an error checker to check the data from the one or more memory devices for errors, the error checker having a first test mode for testing a first aspect of the plurality of memory devices and a second test mode for testing a second aspect of the plurality of memory devices, wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode;

wherein the serial IO test mode is separated from the memory interface test mode; and

wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated by a test generator for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.

2. The memory testing apparatus of claim 1 , further comprising a decoder to translate data from a first data format to a second data format.

3. The memory testing apparatus of claim 2 , wherein the first data format is a format containing a first number of bits and the second data format is a format containing a reduced second number of bits.

4. The memory testing apparatus of claim 1 , wherein data received from the one or more memory devices includes failure information for the one or more memory devices, the one or more memory devices receiving one or more test signals and comparing the received signals using an error checker of a computer memory to determine device failures.

5. The memory testing apparatus of claim 1 , further comprising one or more switching elements to establish a path test signals through the memory devices, the switching elements being controlled by control signals.

6. The memory testing apparatus of claim 1 , further comprising a test pattern source to produce test pattern signals.

7. A method of testing computer memory comprising:

coupling a plurality of memory devices, each of the plurality of devices having:

a differential serializer output including a first serializer node and a second serializer node, and

a differential deserializer input including a first deserializer node and a second deserializer node,

wherein coupling the plurality of memory devices includes:

coupling the first serializer node of a first memory device with the first deserializer node of a second memory device,

coupling the second serializer node of the first memory device with the first deserializer node of the first memory device,

coupling the first serializer node of the second memory device with the second deserializer node of the second memory device, and

coupling the second serializer node of the second memory device with the second deserializer node of the first memory device;

generating test patterns using a test pattern generator for testing of the plurality of memory devices; and

checking data from one or more of the plurality of memory devices for errors using an error checker, the error checker having a first test mode for testing a first aspect of the plurality of memory devices and a second test mode for testing a second aspect of the plurality of memory devices, wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode;

wherein the serial IO test mode is separated from the memory interface test mode; and

wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated by a test generator for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.

8. The method of claim 7 , further comprising translating data from a first data format to a second data format using a decoder.

9. The method of claim 8 , wherein the first data format is a format containing a first number of bits and the second data format is a format containing a reduced second number of bits.

10. The method of claim 7 , wherein data received from the plurality of memory devices includes failure information for the plurality of memory devices, the plurality of memory devices receiving one or more test signals and comparing the received signals using an error checker of a computer memory to determine device failures.

11. The method of claim 7 , further comprising controlling one or more switching elements to establish a path for test signals through the plurality of memory devices, the switching elements being controlled by control signals.