Memory architecture with multiple serial communications ports
View Patent ↗A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
1. A memory device couplable to a plurality of accessing devices, the memory device comprising:
a memory comprising a plurality of banks;
a plurality of ports for accessing the plurality of banks of the memory, each port having a bit serial communications link for receiving from and transmitting to an accessing device where bits of each symbol are received and transmitted serially, each port using a plesiosynchronous technique without transmitting a clock signal to receive symbols and using in-band symbols to transmit data and out-of-band symbols to transmit control information; and
a switch for selectively routing symbols between the plurality of ports and the plurality of banks, wherein the bits of symbols are routed by the switch in parallel.
2. The memory device of claim 1 wherein each bit serial communications link is connected to an accessing device via a point-to-point connection.
3. The memory device of claim 1 wherein the plesiosynchronous technique oversamples data received via the bit serial communications link.
4. A memory device comprising:
a memory; and
a plurality of ports for accessing the memory of the memory device, each port having a serial communications link for receiving from and transmitting to an accessing device, each port using plesiosynchronous technique to receive symbols and using in-band symbols to transmit data and out-of-band symbols to transmit control information wherein each port includes a line driver with a fixed driver portion and a variable driver portion for DC-balancing.
5. The memory device of claim 1 wherein the plurality of banks can be simultaneously accessed by different ports.
6. The memory device of claim 1 wherein each bank includes multiple sections and wherein the multiple sections can be simultaneously accessed by different ports.
7. The memory device of claim 6 wherein the multiple sections of the bank are configurable on a port-by-port basis.
8. The memory device of claim 7 wherein the configuration information indicates to enable certain sections of the bank.
9. The memory device of claim 1 wherein the ports are connected to the memory using time-division multiplexing.
10. The memory device of claim 1 wherein the switch is a crossbar switch.
11. The memory device of claim 1 wherein control information is transmitted as a primitive.
12. The memory device of claim 11 wherein a primitive includes two out-of-band symbols.
13. The memory device of claim 11 wherein control information includes a synchronization symbol.
14. The memory device of claim 1 wherein the plesiosynchronous technique includes inserting or removing symbols to compensate for variations between clock frequencies of the accessing device and the memory device.
15. The memory device of claim 1 wherein the ports share a single multiphase clock generator.
16. The memory device of claim 15 wherein the multiphase clock generator is a phase lock loop.
17. The memory device of claim 1 wherein an out-of-band symbol is a synchronization symbol that encodes a memory command.
18. A memory device comprising: a memory comprising a plurality of banks that reads and writes data; a multiphase clock generator that provides a multiphase clock signal; a plurality of ports for accessing the plurality of banks, each port for connecting to a bit serial communications link, where bits of each symbol are received and transmitted serially, and for receiving data and control information via the bit serial communications link using a plesiosynchronous technique without transmitting a clock signal, wherein each port uses the generated multiphase clock signal generated by the multiphase clock generator; and a switch for selectively routing symbols between the plurality of ports and the plurality of banks, wherein the bits of symbols are routed by the switch in parallel.
19. The memory device of claim 18 wherein data is sent using in-band symbols and control information is sent via out-of-band symbols.
20. The memory device of claim 18 wherein each bit serial communications link is connected to an accessing device via a point-to-point connection.
21. The memory device of claim 18 wherein the plesiosynchronous technique oversamples data received via the bit serial communications link.
22. A memory device comprising: a memory that reads and writes data; a multiphase clock generator that provides a multiphase clock signal; and a plurality of ports, each port for connecting to a serial communications link and for receiving data and control information via the serial communications link using a plesiosynchronous technique, wherein each port uses the generated multiphase clock signal generated by the multiphase clock generator and wherein each port includes a line driver with a fixed driver portion and a variable driver portion for DC-balancing.
23. The memory device of claim 18 wherein the plurality of banks can be simultaneously accessed by different ports.
24. The memory device of claim 18 wherein each bank includes multiple sections and wherein multiple sections can be simultaneously accessed by different ports.
25. The memory device of claim 24 wherein the multiple sections are configurable on a port-by-port basis.
26. The memory device of claim 25 including the configuration information storage.
27. The memory device of claim 18 wherein the ports are connected to the memory using time-division multiplexing.
28. The memory device of claim 18 wherein the switch is a crossbar switch.
29. The memory device of claim 18 wherein control information is transmitted as a primitive.
30. The memory device of claim 29 wherein a primitive includes two out-of-band symbols.
31. The memory device of claim 29 wherein control information includes a synchronization symbol.
32. The memory device of claim 18 wherein the plesiosynchronous technique includes inserting or removing symbols to compensate for variations between clock frequencies of the accessing device and the memory device.
33. The memory device of claim 18 wherein the multiphase clock generator is a phase lock loop.
34. The memory device of claim 18 wherein a synchronization symbol encodes a memory command.