Data synchronization across an asynchronous boundary using, for example, multi-phase clocks
View Patent ↗Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.
1. A retiming circuit for transferring synchronous digital signals across an asynchronous boundary, the retiming circuit comprising:
a first flip-flop having a first data input, a first clock input, and a first output, the first data input coupled to an external clock line, the first clock input coupled to a first phase of an internal clock, the first flip-flop operative to sample a signal on the external clock line according to the first phase of the internal clock;
a second flip-flop having a second data input, a second clock input, and a second output, the second data input coupled to the external clock line, the second clock input coupled to a third phase of the internal clock, the second flip-flop operative to sample the signal on the external clock line according to the third phase of the internal clock;
an inverter having an input and an output, the input coupled to the output of the first flip-flop;
a NAND gate having at least one output providing an output signal and at least two inputs, a first input coupled to the output of the inverter, a second input coupled to the output of the second flip-flop,
a third flip-flop having a third data input, a third clock input, and a third output, the third data input coupled to receive an incoming data signal, the third clock input coupled to a second phase of the internal clock, the third flip-flop operative to sample the incoming data signal according to the second phase of the internal clock; and
a MUX having at least two data inputs, a control input, and an output, a first input coupled to directly receive the incoming data signal, while a second input is coupled to the output of the third flip-flop, and the control input is coupled to the output of the NAND gate, wherein the output of the MUX operative to produce an output signal as an unaltered incoming data signal or an incoming data signal sampled on a rising edge of the second phase of the internal clock depending on the output signal of the NAND gate.
2. The retiming circuit of claim 1 , wherein the retiming circuit further comprises:
a fourth flip-flop having a data input, a clock input, and an output, the data input coupled to receive the output signal of the MUX, and the clock input coupled to the 0 th phase of the internal clock, wherein the fourth flip-flop is operative to sample the output signal of the MUX according to the 0 th phase of the internal clock.
3. A method for transferring synchronous digital signals across an asynchronous boundary separating an external clock domain and an internal clock domain, the method comprising:
sampling an external clock according to a first phase of internal multi-phase clock signals;
sampling the external clock according to a third phase of internal multi-phase clock signals;
determining if the active edge of the external clock is between the active edges of the first and third phases of the internal multi-phase clock signals by inverting the sampled external clock according to the first phase of internal multi-phase clock signal and performing a NAND logical operation on the inverted sample and the sample of the external clock according to the third phase of internal multi-phase clock signal;
sampling an incoming data signal according to the 0 th phase of the internal multi-phase clock signals if the active edge of the external clock is between the active edges of the first and third phases of the internal multi-phase clock signals; and
sampling an incoming data signal according to the second phase of the internal multi-phase clock signals if the active edge of the external clock is not between the active edges of the first and third phases of the internal multi-phase clock signals.
4. A semiconductor chip, comprising:
a first subsystem providing a data signal and operating with respect to at least a first clock signal;
a second subsystem coupled to the first subsystem and having:
a clock signal comparator coupled to receive the first clock signal, wherein the clock signal comparator is configured to compare the first clock signal to at least a second clock signal and produce an output signal in response to the comparison;
a clock signal selector coupled to receive the output signal of the clock signal comparator, wherein the clock signal selector is configured to select one of two or more internal clock signals based on the output signal; and
a sampling component coupled to receive the data signal from the first subsystem and sample the data signal based on the selected clock signal
wherein the clock signal comparator includes an inverter that inverts at least a portion of the first clock signal with respect to the second clock signal, and a NAND gate coupled to receive an output of the inverter and at least a portion of the first clock signal with respect to a third clock signal, wherein the internal clock signals comprise the second and the third clock signals.
5. The semiconductor chip of claim 4 , further comprising a clock signal sample component coupled to the clock signal comparator and configured to sample the first clock signal based on at least the second clock signal.
6. The semiconductor chip of claim 4 , further comprising a clock signal sample component coupled to the clock signal comparator and configured to sample the first clock signal based on at least the second and the third clock signal, wherein the clock signal sample component includes at least first and second D flip-flops that each receive and output a sample of the first clock signal based on the second and third clock signals, respectively.
7. The semiconductor chip of claim 4 wherein the clock signal selector includes a multiplexer coupled to respond to the output signal of the clock signal comparator.
8. The semiconductor chip of claim 4 wherein the sampling component includes:
at least a first D flip-flop configured to receive and output the data signal based on the selected internal clock signal, and
at least a second D flip-flop configured to output either the data signal or an output of the first D flip-flop.
9. The semiconductor chip of claim 4 wherein the sampling component includes at least a first flip-flop configured to receive and output the data signal based on the selected internal clock signal.
10. The semiconductor chip of claim 4 wherein the clock signal comparator is configured to compare active or inactive clock edges of the first clock signal with at least the second clock signal and the third clock signal.
11. The semiconductor chip of claim 4 wherein the clock signal comparator or clock signal selector receive at least the second clock signal and the third clock signal, wherein the second and third clock signals have the same frequency but different phases, and are synchronized with each other.
12. The semiconductor chip of claim 4 wherein the clock signal comparator receives at least the second clock signal and a third clock signal, wherein the second and third clock signals are 180 degrees out of phase with each other.