IP Library Granted Patent US 8,510,487
Granted Patent B2
US 8,510,487 · App. 12/704,417 · Granted Aug 13, 2013

Hybrid interface for serial and parallel communication

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Quick Facts
Patent No.
US 8,510,487
App. No.
12/704,417
Granted
Aug 13, 2013
Kind
B2
Abstract

Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Claims (35)

1. A method comprising:

initializing a first apparatus for transmission of data to or reception of data from a second apparatus, the first apparatus including a reference oscillator circuit;

enabling an interface for the first apparatus initially in a first mode for a parallel interface with the second apparatus, the parallel interface including a first plurality of pins, wherein the parallel interface has a first voltage swing;

transmitting parallel data to the second apparatus or receiving parallel data from the second apparatus in the first mode via the first plurality of pins;

enabling the reference oscillator circuit and enabling the interface of the first apparatus in a second mode for a serial interface with the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, wherein the serial interface has a second voltage swing, the second voltage swing being smaller than the first voltage swing; and

transmitting serial data to the second apparatus or receiving serial data from the second apparatus in the second mode via the second plurality of pins.

2. The method of claim 1 , wherein the parallel interface is not resistively terminated by whichever of the first apparatus or the second apparatus is receiving parallel data.

3. The method of claim 1 , wherein the serial interface is resistively terminated by whichever of the first apparatus or the second apparatus is receiving serial data.

4. The method of claim 1 , wherein the voltage swing for the serial interface is less than one-half of an interface supply voltage.

5. The method of claim 1 , wherein the voltage swing for the serial interface may be set independently of supply voltages for the first and second apparatuses and of termination of the first and second apparatuses.

6. The method of claim 1 , wherein the serial interface uses single-ended signaling.

7. The method of claim 1 , wherein the parallel interface uses single-ended signaling.

8. An apparatus comprising:

an interface for transmission of data to or reception of data from a second apparatus, wherein the interface includes:

a first mode for a parallel interface with the second apparatus, the parallel interface including a first plurality of pins for transmitting parallel data to the second apparatus or receiving parallel data from the second apparatus in the first mode, wherein the parallel interface has a first voltage swing, and

a second mode for a serial interface with the second apparatus, the serial interface including a second plurality of pins for transmitting serial data to the second apparatus or receiving serial data from the second apparatus in the second mode, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, wherein the serial interface has a second voltage swing, the second voltage swing being smaller than the first voltage swing; and

a reference oscillator circuit, wherein for the second mode the reference oscillator circuit is enabled if the reference oscillator circuit is disabled.

9. The apparatus of claim 8 , wherein the parallel interface is not resistively terminated by whichever of the apparatus and the second apparatus is receiving parallel data.

10. The apparatus of claim 8 , wherein the serial interface is resistively terminated by whichever of the apparatus and the second apparatus is receiving serial data.

11. The apparatus of claim 8 , wherein the voltage swing for the serial interface is less than one-half of an interface supply voltage.

12. The apparatus of claim 8 , wherein the voltage swing for the serial interface may be set independently of supply voltages for the first and second apparatuses and of termination of the first and second apparatuses.

13. The apparatus of claim 8 , wherein the serial interface uses single-ended signaling.

14. The apparatus of claim 8 , wherein the parallel interface uses single-ended signaling.

15. A computer-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

initializing a first apparatus for transmission of data to or reception of data from a second apparatus, the first apparatus including a reference oscillator circuit;

enabling an interface for the first apparatus initially in a first mode for a parallel interface with the second apparatus, the parallel interface including a first plurality of pins, wherein the parallel interface has a first voltage swing;

transmitting parallel data to the second apparatus or receiving parallel data from the second apparatus in the first mode via the first plurality of pins;

enabling the reference oscillator circuit and enabling the interface of the first apparatus in a second mode for a serial interface with the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, wherein the serial interface has a second voltage swing, the second voltage swing being smaller than the first voltage swing; and

transmitting serial data to the second apparatus or receiving serial data from the second apparatus in the second mode via the second plurality of pins.

16. The medium of claim 15 , wherein the parallel interface is not resistively terminated by whichever of the first apparatus or the second apparatus is receiving parallel data.

17. The medium of claim 15 , wherein the serial interface is resistively terminated by whichever of the first apparatus or the second apparatus is receiving serial data.

18. The medium of claim 15 , wherein the voltage swing for the serial interface is less than one-half of an interface supply voltage.

19. The medium of claim 15 , wherein the voltage swing for the serial interface may be set independently of supply voltages for the first and second apparatuses and of termination of the first and second apparatuses.

20. The medium of claim 15 , wherein the serial interface uses single-ended signaling.

21. The medium of claim 15 , wherein the parallel interface uses single-ended signaling.

Assignments (6)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2015
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036905/0327 →
MERGER Recorded Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
SECURITY INTEREST Recorded Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0289 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2010
From: RUBERG, ALAN T.; ISAAC, ROGER D.
To: SILICON IMAGE, INC.
Reel/Frame 024248/0721 →