Computer memory test structure

1. A method of testing a device, the method comprising:

testing a device including a component, the device including a plurality of serial ports,

testing of the component including:

providing, by a first built-in self-test structure of the component a first test pattern for the testing of the component, wherein the first test pattern complies with a protocol for the component;

performing error checking for the testing of the component by enabling detection of legal commands for the component; and

testing a serial interface of the device, testing of the serial interface including:

providing, by the first built-in self-test structure of the component, a second test pattern for the testing of the serial interface;

wherein testing of the component is separate from the testing of the serial interface.

2. The method of claim 1 , wherein the component includes one or more memories.

3. The method of claim 2 , wherein the one or more memories are serial port dynamic random access memories.

4. The method of claim 1 , wherein the first built-in self-test structure includes a set of interface test structures for the component and a set of interface structures for the serial interface.

5. The method of claim 1 , wherein the second test pattern for the testing of the serial interface does not comply with the protocol for the component.

6. The method of claim 1 , further comprising encoding a test property into the second test pattern.

7. The method of claim 1 , wherein the serial interface is between the component and a host, the host further including a second built-in self-test structure, and wherein testing further includes use of the second built-in self-test structure of the host.

8. The method of claim 1 , further comprising examining a received test pattern to determine if one or more errors have occurred in the component or the serial interface.

9. The method of claim 1 , further comprising testing of the component based on checking an extracted test property of the first test pattern.

10. The method of claim 1 , wherein providing the first test pattern and the second test pattern includes generation of test signals.

11. The method of claim 1 , wherein providing the first test pattern and the second test pattern includes receipt of test signals from an external tester.

12. The method of claim 1 , further comprising bypassing at least a part of the first built-in self-test structure to loop back a signal for testing.

13. The method of claim 1 , further comprising coupling the plurality of serial ports of the device together for testing.

14. The method of claim 13 , wherein each port of the plurality of ports of the component includes a serializer and a deserializer, wherein coupling the ports together includes connecting the serializer of a first port to a deserializer of a second port.

15. The method of claim 14 , wherein testing includes applying a test pattern to the serializer of the first port and receiving a test pattern at a deserializer for the first port.

16. The method of claim 14 , wherein a first port and a second port coupled together are each bidirectional on a pin, and wherein the first port is configured to transmit and the second port is configured to receive.

17. The method of claim 1 , further comprising:

generating a test pattern utilizing a plurality of hierarchically organized test encoding functions to embed a test property into the test pattern.

18. The method of claim 1 , wherein testing of the component and of the serial interface are tested internally in the device, testing including configuring the device to loop back a signal.

19. The method of claim 1 , wherein testing the serial interface includes looping back a signal from an output of the device to an input of the device.

20. The method of claim 1 , wherein testing the serial interface includes looping back a signal within a host connected to the component from an input of the host to an output of the host.

21. The method of claim 1 , wherein the component includes a plurality of elements,

and wherein testing of the component includes testing of an interface of each of the plurality of elements.

22. The method of claim 21 , wherein the testing of the interface for each of the plurality of elements includes switching one or more links of each interface on or off to generate a test path for transmission of a test pattern.

23. The method of claim 22 , wherein the switching of one of more links includes switching to generate a non-functional test path.

24. The method of claim 22 , wherein the switching of one or more links includes switching links to test for one or more of open faults and bridging faults.

25. An apparatus including:

a component including:

a first built-in self-test structure, wherein the first built-in self-test structure includes a first set of component test structures and a second set of serial interface test structures, and

a plurality of ports; and

a serial interface for the component;

wherein the component and the serial interface are to be tested using the a first set of component test structures and a second set of serial interface test structures, and wherein testing of the component includes providing by the first built-in self-test structure a first test pattern for the component, the first test pattern complying with a protocol for the component, and testing of the interface includes providing by the first built-in self-test structure a second test pattern for the serial interface; and

wherein the testing of the component and the serial interface are run separately.

26. The apparatus of claim 25 , wherein the component includes one or more memories.

27. The apparatus of claim 26 , wherein the one or more memories are serial port dynamic random access memories (SPDRAM).

28. The apparatus of claim 25 , wherein the second test pattern does not comply with the protocol for the component.

29. The apparatus of claim 25 , wherein each port of the plurality of serial ports has a serializer and a deserializer.

30. The apparatus of claim 25 , wherein a test generator generates a test pattern for each port of the plurality of ports of the component.

31. The apparatus of claim 25 , wherein each port of the plurality of ports includes an error checker, each error checker checking the test patterns received by a deserializer for the respective port.

32. The apparatus of claim 25 , further comprising a physical layer of a host, the physical layer includes a second built-in self-test structure.

33. The apparatus of claim 25 , wherein the apparatus includes a single error checker for the plurality of ports.

34. The apparatus of claim 25 , wherein the plurality of ports are connected together serially for testing of the apparatus.

35. A non-transitory computer-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

testing a device including a component, the device including a plurality of serial ports,

testing of the component including:

providing, by a first built-in self-test structure of the component a first test pattern for the testing of the component, wherein the first test pattern complies with a protocol for the component;

performing error checking for the testing of the component by enabling detection of legal commands for the component; and

testing a serial interface of the device, testing of the serial interface including:

providing, by the first built-in self-test structure of the component, a second test pattern for the testing of the serial interface;

wherein testing of the component is separate from the testing of the serial interface.

36. The medium of claim 35 , wherein the component includes one or more memories.

37. The medium of claim 36 , wherein the one or more memories are serial port dynamic random access memories (SPDRAM).