Determining oversampled data to be included in unit intervals
View Patent ↗In some embodiments, a chip includes sampling circuitry to produce oversampled data from a received signal, and logic to determine which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals. Other embodiments are described and claimed.
1. A chip comprising:
sampling circuitry to produce oversampled data from a received signal; and
logic to determine which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals.
2. The chip of claim 1 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
3. The chip of claim 2 , wherein the oversampled data are arranged in lines and for some of the determinations, the section is in one of the lines and the additional oversampled data is in another of the lines.
4. The chip of claim 2 , wherein the logic includes stages in a pipeline and wherein the oversampled data are arranged in lines that are advanced through the stages and wherein the logic concurrently evaluates different sections of the oversampled data in different lines.
5. The chip of claim 4 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
6. The chip of claim 5 , wherein for some of the determinations, the section is a last group of the oversampled data of its line, and the additional oversampled data is a first group of the oversampled data of the next line in time order.
7. The chip of claim 4 , wherein the lines of oversampled data are held in the stages in an order based on when the oversampled data is created so that the first line to be created is the first to pass through the pipeline.
8. The chip of claim 4 , wherein at least one section of a line being evaluated in a particular stage is identified within the stage by a pointer, and wherein as a line advances in the pipeline, the pointer moves toward an end of the line by an amount equal to the number of oversampled data that were found by the previous stage to be included in a unit interval.
9. The chip of claim 4 , wherein some of the stages later in the pipeline have a smaller capacity than some of the stages earlier in the pipeline.
10. The chip of claim 4 , wherein the oversampled data being evaluated in line shifts its relative position within a stage as the line advances through at least some of the stages.
11. The chip of claim 4 , wherein the logic further determines values of output bits based on content of the unit intervals, and wherein each line typically provides a particular number of bits as it passes through all the stages, and if lines provide more than the particular number of bits a certain number of times, then that fact is considered in determinations for future lines until a future line provides less than the particular number of bits, and if a line provides less than the particular number of bits a certain number of times, then that fact is considered in determinations for future lines until a future line provides more than the particular number of bits.
12. The chip of claim 4 , wherein the lines have 50 oversampled data, there are typically 5 oversampled data per unit interval, and on average there are 10 output bits in the 50 oversampled data.
13. The chip of claim 4 , wherein the logic uses tables to help with the determinations.
14. The chip of claim 4 , wherein logic includes prefiltering to alter the values of some of the oversampled data prior to the determinations.
15. A method comprising:
sampling a received signal to produce oversampled data; and
determining which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals.
16. The method of claim 15 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
17. The method of claim 16 , wherein the oversampled data are arranged in lines and for some of the determinations, the section is in one of the lines and the additional oversampled data is in another of the lines.
18. The method of claim 15 , wherein the logic includes stages in a pipeline and wherein the oversampled data are arranged in lines that are advanced through the stages and wherein the logic concurrently evaluates different sections of the oversampled data in different lines.
19. The method of claim 15 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
20. The method of claim 19 , wherein for some of the determinations, the section is a last group of the oversampled data of its line, and the additional oversampled data is a first group of the oversampled data of the next line in time order.
21. A system comprising:
conductors;
a first chip include transmitters to transmit data to the conductors; and
a second chip to receive the transmitted data from the conductors, the second chip having processing circuitry including:
sampling circuitry to produce oversampled data from a received signal; and
logic to determine which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals.
22. The system of claim 21 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data having the typical number of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
23. The system of claim 22 , wherein the oversampled data are arranged in lines and for some of the determinations, the section is in one of the lines and the additional oversampled data is in another of the lines.
24. The system of claim 22 , wherein the logic includes stages in a pipeline and wherein the oversampled data are arranged in lines that are advanced through the stages and wherein the logic concurrently evaluates different sections of the oversampled data in different lines.
25. The system of claim 24 , wherein for at least some of the determinations, the logic evaluates a section of oversampled data having the typical number of oversampled data and looks ahead by also evaluating additional oversampled data occurring after the section in time order.
26. The system of claim 25 , wherein for some of the determinations, the section is a last group of the oversampled data of its line, and the additional oversampled data is a first group of the oversampled data of the next line in time order.
27. The system of claim 21 , wherein the processing circuitry further determines values of output bits based on content of the unit intervals and provides output signals responsive thereto, and wherein the system further comprises a display that receives at least some of the output signals.