Error detection in physical interfaces for point-to-point communications between integrated circuits
View Patent ↗An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.
1. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”), the apparatus comprising:
an N bit/(N+2) bit physical layer (“PHY”) encoder configured to:
insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and
encode said N+1 unencoded data bits to yield N+2 encoded data bits; and
an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit,
wherein N represents any integer number of data bits.
2. The apparatus of claim 1 , further comprising a serializer configured to serialize said N+2 encoded data bits to form serial N+2 encoded data bits, thereby interleaving error-detection data bits with other data bits.
3. The apparatus of claim 1 , further comprising storage to store a group of data bits that include said N application data bits, said error-detection code generator being configured to examine said group of data bits to generate said error-detection code.
4. The apparatus of claim 3 , further comprising a transmitter error corrector configured to retransmit one or more subsets of said group of data bits when said transmitter error corrector receives a request for retransmission.
5. The apparatus of claim 1 , wherein N is one of 8, 12, 18, 64 and 128.