CMOS transceiver with dual current path VCO
View Patent ↗A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10 −12 bit error rate up to speeds of 3 Gbps.
1. A quad-channel transceiver comprising:
a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal;
a FIFO buffer used to store data to be transmitted;
a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and
a folded starved inverter circuit contained within the voltage controlled oscillator, the folded starved inverter circuit provides two current paths and contains four transistors connected to provide the folded starved inverter circuit, wherein two of the four transistors provide an input connection, and two of the four transistors provide a current controlling function.
2. The quad-channel transceiver of claim 1 wherein the transceiver further comprises a FIFO buffer control circuit.
3. The quad-channel transceiver of claim 1 wherein the transceiver further comprises a delay locked loop.
4. The quad-channel transceiver of claim 3 wherein the delay locked loop further comprises a coarse phase detector and a fine phase detector.
5. The quad-channel transceiver of claim 4 wherein the delay locked loop sends a signal to a FIFO buffer control circuit.
6. A quad-channel transceiver comprising:
a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal;
a FIFO buffer used to store data to be transmitted;
a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit;
a folded starved inverter circuit and a low pass filter network contained within the voltage controlled oscillator; and
the low pass filter network comprises two capacitors and one resistor.
7. The quad-channel transceiver of claim 6 wherein the folded starved inverter circuit provides a coarse tracking current path and a fine tracking current path, and the coarse tracking current path and fine tracking current path are linearly merged.
8. A method for operating a quad-channel transceiver comprising:
providing data to be transmitted into a FIFO buffer;
providing clock signals using a phase locked loop and voltage controlled oscillator circuits;
providing a plurality of delayed clock signals; and
transmitting data using clock signals produced from a folded starved inverter circuit contained within the voltage controlled oscillator circuit;
wherein the folded starved inverter circuit contains two current paths and contains four transistors connected to provide the folded starved inverter circuit, wherein two of the four transistors provide an input connection, and two of the four transistors provide a current controlling function.
9. The method for operating a quad-channel transceiver of claim 8 wherein the plurality of delayed clock signals are provided by a delay locked loop.
10. The method for operating a quad-channel transceiver of claim 9 wherein the delay locked loop further comprises a coarse phase detector and a fine phase detector.
11. A quad-channel transceiver comprising:
a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal;
a FIFO buffer used to store data to be transmitted by a quad-channel transmitter component within the quad-channel transceiver; and
a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit;
the voltage controlled oscillator further including:
(i) a folded starved inverter circuit that includes two current paths and that provides a coarse tracking current path and a fine tracking current path that are linearly merged;
(ii) at least two transistors cross-coupled to provide a differential output stage; and
(iii) a low pass filter network including at least two capacitive elements and at least one resistive element.
12. A quad-channel transceiver as in claim 11 , wherein the quad-channel transceiver comprises a quad-channel transmitter.
13. A method for operating a quad-channel transceiver comprising:
providing data to be transmitted by a quad-channel transmitter component of the quad-channel transceiver into a FIFO buffer;
generating clock signals using a phase locked loop and voltage controlled oscillator circuits;
generating a plurality of delayed clock signals using at least one delay locked loop circuit, the at least one delay locked loop circuit including a coarse phase detector detecting a coarse phase and a fine phase detector detecting a fine phase; and
transmitting data from the quad-channel transmitter component within the quad-channel transceiver using clock signals produced from a folded starved inverter circuit contained within the voltage controlled oscillator circuit providing two current paths and including four transistors wherein two of the four transistors provide a current controlling function and further providing a coarse tracking current path and a fine tracking current path that are linearly merged.