IP Library Granted Patent US 7,058,121
Granted Patent B1
US 7,058,121 · App. 09/989,647 · Granted Jun 6, 2006

Logic gates including diode-connected metal-oxide-semiconductor field-effect transistors (MOSFETS) to control input threshold voltage levels and switching transients of output logic signals

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Quick Facts
Patent No.
US 7,058,121
App. No.
09/989,647
Granted
Jun 6, 2006
Kind
B1
Abstract

Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.

Claims (44)

1. A data communications system including a bidirectional buffer coupled among a transmitter, a receiver, and a transmission line, wherein the bidirectional buffer comprises an output differential amplifier section that generates an output logic signal from positive polarity data signals and negative polarity data signals received from the transmitter and the transmission line, wherein the output logic signal represents data received on the transmission line, wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate with a higher logic threshold voltage than a mid-supply voltage of the output differential amplifier section, wherein a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) is placed in a ground path of the at least one logic gate.

2. A bidirectional bridge circuit for interfacing between a transmission line and a communication device, the bidirectional bridge circuit comprising an output differential amplifier coupled to receive inputs including positive polarity data signals and negative polarity data signals and generate an output logic signal representative of data received via the transmission line,

wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a threshold voltage that differs from a mid-supply voltage of the output differential amplifier.

3. A bidirectional bridge circuit for interfacing between a transmission line and a communication device, the bidirectional bridge circuit comprising an output differential amplifier coupled to receive inputs including positive polarity data signals and negative polarity data signals and generate an output logic signal representative of data received via the transmission line,

wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a higher input threshold voltage than a mid-supply voltage of the output differential amplifier, wherein a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) is placed in a ground path of the at least one logic gate.

4. A bidirectional bridge circuit for interfacing between a transmission line and a communication device, the bidirectional bridge circuit comprising an output differential amplifier coupled to receive inputs including positive polarity data signals and negative polarity data signals and generate an output logic signal representative of data received via the transmission line,

wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a lower input threshold voltage than a mid-supply voltage of the output differential amplifier, wherein a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) is placed in a supply path of the at least one logic gate.

5. A bidirectional bridge circuit for interfacing between a transmission line and a communication device, the bidirectional bridge circuit comprising an output differential amplifier coupled to receive inputs including positive polarity data signals and negative polarity data signals and generate an output logic signal representative of data received via the transmission line, wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a threshold voltage that differs from a mid-supply voltage of the output differential amplifier,

wherein the output differential amplifier comprises a NAND logic gate with a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) in a ground path, wherein a logic threshold voltage of the NAND logic gate is higher than a mid-supply voltage while switching rise and fall times are maintained as approximately symmetric.

6. A method for providing a bidirectional communications interface including a bridge connecting a transmitter and a receiver to a transmission line, the method comprising:

receiving differential pairs of signals from the transmission line and the transmitter;

generating an output logic signal to the receiver; and

controlling symmetry in switching transients of the output logic signal by increasing a logic threshold voltage of a logic gate of an output amplifier above a mid-supply voltage of the logic gate.

7. A bi-directional bridge circuit comprising:

a first amplifier with an input coupled to a signal source and an output coupled to a transmission line;

a second amplifier with an input coupled to the signal source and an output coupled to a common mode feedback differential amplifier;

the common mode feedback differential amplifier with a first input coupled to the output of the second amplifier, a second input coupled to the transmission line and an output coupled to an asymmetric differential amplifier;

the asymmetric differential amplifier with an input coupled to the output of the common mode feedback differential amplifier and an output coupled to an outgoing signal line;

a differential amplifier with a first input coupled to the output of the second amplifier, a second input coupled to the transmission line, a third input coupled to an output of a common mode feed back circuitry and an output coupled to an input of the asymmetric differential amplifier; and

the common mode feed back circuitry with a first input coupled to the output of the second amplifier, a second input coupled to the transmission line and the output coupled to the third input of the differential amplifier.

8. A bi-directional bridge circuit comprising:

a first amplifier with an input coupled to a signal source and an output coupled to a transmission line;

a second amplifier with an input coupled to the signal source and an output coupled to a common mode feedback differential amplifier;

the common mode feedback differential amplifier with a first input coupled to the output of the second amplifier, a second input coupled to the transmission line and an output coupled to an asymmetric differential amplifier; and

the asymmetric differential amplifier with an input coupled to the output of the common mode feedback differential amplifier and an output coupled to an outgoing signal line;

wherein the asymmetric differential amplifier generates an output logic signal representative of data received via the transmission line wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a threshold voltage that differs from a mid-supply voltage of the asymmetric differential amplifier.

9. The bidirectional bridge circuit as recited in claim 8 wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a higher input threshold voltage than a mid-supply voltage of the asymmetric differential amplifier, wherein a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) is placed in a ground path of the at least one logic gate.

10. The bidirectional bridge circuit as recited in claim 8 wherein symmetry is controlled in switching transients of the output logic signal using at least one logic gate having a lower input threshold voltage than a mid-supply voltage of the asymmetric differential amplifier, wherein a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) is placed in a supply path of the at least one logic gate.

11. The bi-directional bridge circuit as recited in claim 8 wherein the asymmetric differential amplifier comprises a NAND logic gate with a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) in a ground path, wherein a logic threshold voltage of the NAND logic gate is higher than a mid-supply voltage while switching rise and fall times are maintained as approximately symmetric.

12. The bi-directional bridge circuit as recited in claim 8 wherein the logic gate having a threshold voltage that differs from a mid-supply voltage level, comprising a diode-connected metal-oxide-semiconductor field effect transistor (MOSFET) in a component path of the logic gate to control a threshold voltage level, wherein symmetry is controlled in switching transients of output logic signals of the logic gate.

13. The bi-directional bridge circuit as recited in claim 12 wherein the logic gate is a NAND gate, wherein the diode-connected MOSFET is an n-type MOSFET placed in a ground path of the logic gate, wherein the threshold voltage level is higher than the mid-supply voltage level.

14. The bidirectional bridge circuit as recited in claim 12 wherein the logic gate is a NAND gate, wherein the diode-connected MOSFET is a p-type MOSFET placed in a supply voltage path of the logic gate, wherein the threshold voltage level is lower than the mid-supply voltage level.

15. A bidirectional communication link, comprising:

means for receiving differential signal pairs from transmission lines and transmitters;

means for generating an output logic signal from the differential data signal pairs, wherein the output logic signal represents data received in the transmission line differential signal pairs;

means for controlling symmetry in switching transients of the output logic signal by increasing a logic threshold voltage of a logic gate of the means for generating an output logic signal above a mid-supply voltage using a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) in a ground path; and

means for coupling the output logic signal to a receiver;

wherein the logic gate is a NAND gate, wherein the diode-connected MOSFET is an n-type MOSFET placed in a ground path of the logic gate, wherein the threshold voltage level is higher than the mid-supply voltage level.

16. A bi-directional communication link, comprising:

means for receiving differential signal pairs from transmission lines and transmitters;

means for generating an output logic signal from the differential data signal pairs, wherein the output logic signal represents data received in the transmission line differential signal pairs;

means for controlling symmetry in switching transients of the output logic signal by increasing a logic threshold voltage of a logic gate of the means for generating an output logic signal above a mid-supply voltage using a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) in a ground path; and

means for coupling the output logic signal to a receiver;

wherein the logic gate is a NAND gate, wherein the diode-connected MOSFET is a p-type MOSFET placed in a supply voltage path of the logic gate, wherein the threshold voltage level is lower than the mid-supply voltage level.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2021
From: LATTICE SEMICONDUCTOR CORPORATION
To: UNIVERSAL CONNECTIVITY TECHNOLOGIES INC.
Reel/Frame 058979/0440 →
RELEASE OF SECURITY INTEREST Recorded Nov 10, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 058067/0896 →
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
MERGER Recorded Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
SECURITY INTEREST Recorded Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0147 →