IP Library Granted Patent US 7,225,282
Granted Patent B1
US 7,225,282 · App. 10/171,820 · Granted May 29, 2007

Method and apparatus for a two-wire serial command bus interface

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Quick Facts
Patent No.
US 7,225,282
App. No.
10/171,820
Granted
May 29, 2007
Kind
B1
Abstract

A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Claims (62)

1. A method for bi-directional transmission of data between a source and a sink over a two-wire interface comprising:

re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal;

transmitting the different protocol signal from the source to the sink over the two-wire interface;

re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink;

re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and

transmitting the different protocol signal from the sink to the source over the two-wire interface.

2. The method as recited in claim 1 wherein the sink initiates transmission of data to the source.

3. The method as recited in claim 1 or 2 further comprising a logic that determines if the source and the sink are capable of re-mapping the different protocol signal into the data signal and the clock signal.

4. The method as recited in claim 3 wherein the logic directs the source to transmit the data signal and the clock signal over the two-wire interface if the sink is incapable of re-mapping the different protocol signal into the data signal and the clock signal.

5. The method as recited in claim 3 wherein the logic directs the sink to transmit the data signal and the clock signal over the two-wire interface if the source is incapable of re-mapping the different protocol signal into the data signal and the clock signal.

6. The method as recited in claim 3 wherein the logic directs the source to transmit the different protocol signal over the two-wire interface if the sink is capable of re-mapping the different protocol signal into the data signal and the clock signal.

7. The method as recited in claim 3 wherein the logic directs the sink to transmit the different protocol signal over the two-wire interface if the source is capable of re-mapping the different protocol signal into the data signal and the clock signal.

8. The method as recited in claim 3 further comprising a set of control registers located on the sink wherein the set of control registers define a list of devices and an associated list of capabilities.

9. The method as recited in claim 8 wherein the logic determines if the sink is capable of re-mapping the different protocol signal into the data signal and the clock signal by:

directing the source to transmit the data signal and the clock signal over the two-wire interface to the sink;

soliciting the set of control registers for the list of devices and the associated list of capabilities; and

directing the source to transmit the different protocol signal if every device from the list of devices is capable of re-mapping the different protocol signal.

10. The method as recited in claim 9 wherein the logic directs the source to transmit the data signal and the clock signal if at least one device from the list of devices is incapable of re-mapping the different protocol signal.

11. The method as recited in claim 8 wherein the logic determines if the source is capable of re-mapping the different protocol signal into the data signal and the clock signal by:

directing the sink to transmit the data signal and the clock signal over the two-wire interface to the source;

soliciting the set of control registers for the list of devices and the associated list of capabilities; and

directing the sink to transmit the different protocol signal if every device from the list of devices is capable of re-mapping the different protocol signal.

12. The method as recited in claim 11 wherein the logic directs the sink to transmit the data signal and the clock signal if at least one device from the list of devices is incapable of re-mapping the different protocol signal.

13. The method as recited in claim 3 wherein the logic determines if the sink is capable of processing the second format data signal and the second format clock signal by:

directing the source to transmit the different protocol signal over the two-wire interface to the sink; and

directing the source to continue transmitting the different protocol signal if the sink transmits the different protocol signal over the two-wire interface back to the source.

14. The method as recited in claim 13 wherein the logic directs the source to transmit the data signal and the clock signal if the sink does not transmit the different protocol signal over the 2-wire interface back to the source.

15. The method as recited in claim 3 wherein the logic determines if the source is capable of processing the second format data signal and the second format clock signal by:

directing the sink to transmit the different protocol signal over the two-wire interface to the source; and

directing the sink to continue transmitting the different protocol signal if the source transmits the different protocol signal over the two-wire interface back to the sink.

16. The method as recited in claim 15 wherein the logic directs the sink to transmit the data signal and the clock signal if the source does not transmit the different protocol signal over the 2-wire interface back to the sink.

17. The method as recited in claim 2 further comprising a logic that adaptively determines a type of different protocol signal that the sink is capable of processing.

18. The method as recited in claim 17 wherein the logic adaptively determines the type of different protocol signal by:

directing the source to transmit a default protocol signal over the two-wire interface to the sink;

monitoring a two-wire interface for a responding protocol signal;

receiving the responding protocol signal over the two-wire interface from the sink;

determining if the default protocol signal and the responding protocol signal differs; and

directing the source to transmit the responding protocol signal over the two-wire interface to the sink if the default protocol signal and the responding protocol signal differ and if the logic recognizes the responding protocol signal.

19. The method as recited in claim 18 wherein the logic directs the source to transmit the default protocol signal if the default protocol signal and the responding protocol signal do not differ.

20. The method as recited in claim 18 wherein the logic monitors for a response from the sink if the default protocol signal and the responding protocol signal differs and if the logic does not recognize the responding protocol signal.

21. The method as recited in claim 2 further comprising a logic that adaptively determines a type of different protocol signal that the source is capable of processing.

22. The method as recited in claim 21 wherein the logic adaptively determines the type of different protocol signal by:

directing the sink to transmit a default protocol signal over the two-wire interface to the source;

monitoring a two-wire interface for a responding protocol signal;

receiving the responding protocol signal over the two-wire interface from the source;

determining if the default protocol signal and the responding protocol signal differs; and

directing the sink to transmit the responding protocol signal over the two-wire interface to the source if the default protocol signal and the responding protocol signal differ and if the logic recognizes the responding protocol signal.

23. The method as recited in claim 22 wherein the logic directs the sink to transmit the default protocol signal if the default protocol signal and the responding protocol signal do not differ.

24. The method as recited in claim 22 wherein the logic monitors for a response from the source if the default protocol signal and the responding protocol signal differs and if the logic does not recognize the responding protocol signal.

25. The method as recited in claim 2 wherein the logic performs a firewall function by closing access to the two-wire interface.

26. The method as recited in claim 2 wherein the source and the sink both further comprise a buffer.

27. The method as recited in claim 26 wherein the logic performs a firewall function by closing access to the two-wire interface.

28. The method as recited in claim 1 wherein the source is a computer and the sink is a monitor.

29. The method as recited in claim 1 wherein the source is a video source and the sink is a monitor.

30. The method as recited in claim 29 wherein the video source is a DVD player.

31. The method as recited in claim 29 wherein the video source is a video cassette recorder.

32. The method as recited in claims 28 , 29 , 30 or 31 wherein the monitor is a television.

33. The method as recited in claim 1 wherein the different protocol signal is defined in an ethernet protocol.

34. The method as recited in claim 1 wherein the different protocol signal is defined in a TCP/IP protocol.

35. The method as recited in claim 1 wherein the different protocol signal is defined in an RS-232 protocol.

36. The method as recited in claim 1 wherein the different protocol signal is defined in a current loop protocol.

37. The method as recited in claims 1 or 2 wherein the data signal, the clock signal and the different protocol signal are transmitted over the two-wire interface simultaneously.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2024
From: KONINKLIJKE PHILIPS N.V.
To: GENERAL VIDEO, LLC
Reel/Frame 067912/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: KONINKLIJKE PHILIPS N.V.
Reel/Frame 050314/0434 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
MERGER Recorded Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
SECURITY INTEREST Recorded Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0147 →