IP Library Granted Patent US 9,887,733
Granted Patent B2
US 9,887,733 · App. 15/582,371 · Granted Feb 6, 2018

Calibration for echo cancellation in a full duplex communication system

Inventors: Kai Zhou (Shanghai, CN); Shinje Tahk (Sunnyvale, CA); Kai Lei (Shanghai, CN); Qiming Wu (Shanghai, CN); Gijung Ahn (San Jose, CA); Min-Kyu Kim (Sunnyvale, CA); Fei Song (Shanghai, CN); Kexin Luo (Shanghai, CN)
Assignee: Lattice Semiconductor Corporation
H04B3/232H04L5/0091H04L5/14
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Quick Facts
Patent No.
US 9,887,733
App. No.
15/582,371
Granted
Feb 6, 2018
Kind
B2
Abstract

A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

Claims (16)

1. A device for full duplex communication over a channel, comprising:

a driver circuit configured to generate a reference signal;

a replica driver circuit configured to generate a calibration signal; and

a calibration circuit coupled to the driver circuit and the replica driver circuit and configured to:

determine a first reference voltage,

adjust an amplitude of the calibration signal linearly,

record a first amplitude value and a second amplitude value of the amplitude of the calibration signal responsive to determining that a first difference between the amplitude of the calibration signal and an amplitude of the reference signal is equal to the first reference voltage, and

determine a calibration amplitude by averaging the first amplitude and the second amplitude values.

2. The device of claim 1 , wherein the calibration module circuit is further configured to:

determine a second reference voltage,

adjust a transition time of the calibration signal linearly,

record a first transition time value and a second transition time value of the calibration signal responsive to determining that a second difference between the amplitude of the calibration signal and the amplitude of the reference signal is equal to the second reference voltage, and

determine a calibration transition time by averaging the first transition time and the second transition time.

3. The device of claim 2 , wherein the calibration circuit comprises a digital-to-analog converter configured to generate the first reference voltage and the second reference voltage, and a comparator circuit configured to compare the difference of the calibration signal and the reference signal to the first reference voltage or the second reference voltage.

4. The device of claim 1 , wherein the calibration circuit determines that the first difference is equal to the first reference voltage responsive to detecting that a pattern of alternating zeros and ones in the first difference disappears.

5. The device of claim 2 , wherein the calibration circuit determines that the second difference is equal to the second reference voltage responsive to detecting that a pattern of alternating zeros and ones in the second difference disappears.

Assignments (3)
SECURITY INTEREST Recorded Jul 18, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049795/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2017
From: ZHOU, KAI; TAHK, SHINJE; LEI, KAI; WU, QIMING; KIM, MIN-KYU; SONG, FEI; LUO, KEXIN; AHN, GIJUNG
To: SILICON IMAGE, INC.
Reel/Frame 042745/0783 →
MERGER Recorded Jun 19, 2017
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 042750/0578 →
Continuity (2)
Continuation 14440589
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