Method and system for transmitting or receiving N-bit video data over a serial link

1. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the sequence of K-bit fragments is a sequence of M-fragment groups, each of the fragments in each of the groups has a different phase within the group, the circuitry is configured to recover the K-bit words of video data during active video intervals and to recover packing phase data that have been transmitted to at least some of the inputs during at least some blanking intervals between the active video intervals, the packing phase data indicate the phase of one of the fragments transmitted at a known checkpoint, and the circuitry is configured to generate at least one control bit in response to the packing phase data and to assert each said control bit to the subsystem to set said subsystem in a state corresponding to said phase of said one of the fragments transmitted at the known checkpoint.

2. The receiver of claim 1 , wherein the packing phase data recovered during each blanking interval indicate the phase of the last one of the fragments transmitted before said blanking interval, and the circuitry is configured to generate the at least one control bit in response to the packing phase data and to assert each said control bit to the subsystem to set said subsystem in a state corresponding to said phase of the last one of the fragments transmitted before said blanking interval.

3. The receiver of claim 2 , wherein the circuitry is configured to recover color mode data that have been transmitted to at least some of the inputs during at least some blanking intervals between the active video intervals to indicate in which N-bit mode the receiver should operate, and the circuitry is configured to generate at least one control bit in response to the color mode data and to assert each said control bit to the subsystem.

4. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the circuitry is also configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, and the circuitry includes a frequency divider coupled to receive the link clock and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the link clock.

5. The receiver of claim 4 , wherein the subsystem includes a FIFO coupled to receive the link clock and the pixel clock, and the subsystem is configured to clock the fragments into the FIFO in response to the link clock and to clock the sequence N-bit video data words out of the FIFO in response to the pixel clock.

6. The receiver of claim 1 , wherein the circuitry is configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data.

7. The receiver of claim 6 , wherein K=8, the link is a transition minimized differential signaling (TMDS) link, the circuitry is configured to recover 10-bit TMDS code words indicative of the 8-bit words of video data and to decode the TMDS code words to recover the 8-bit words of video data.

8. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the circuitry is configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data, and

wherein K=8, the receiver is operable in a 10-bit mode in which N=10, the sequence of 8-bit fragments is a sequence of groups, each said group consists of five of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 10-bit mode to generate a pixel clock having frequency P at least substantially equal to (4/5)L in response to the link clock, and the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a third fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters a first intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters a second intermediate state;

during a third cycle of the link clock in the blanking interval, the receiver enters a third intermediate state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters a first blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a second blanking state, a third blanking state, a fourth blanking state, a fifth blanking state, and the first blanking state.

9. The receiver of claim 8 , wherein the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a third fragment of a group has been asserted to the subsystem but before a fourth fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters the second intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters the third intermediate state;

during a third cycle of the link clock in the blanking interval, the receiver enters the first blanking state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters the second blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of the third blanking state, the fourth blanking state, the fifth blanking state, the first blanking state, and the second blanking state.

10. The receiver of claim 9 , wherein the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a fourth fragment of a group has been asserted to the subsystem but before a fifth fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters the third intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters the first blanking state;

during a third cycle of the link clock in the blanking interval, the receiver enters the second blanking state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters the third blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of the fourth blanking state, the fifth blanking state, the first blanking state, the second blanking state, and the third blanking state.

11. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the circuitry is configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data, and

wherein K=8, the receiver is operable in a 12-bit mode in which N=12, the sequence of 8-bit fragments is a sequence of groups, each said group consists of three of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 12-bit mode to generate a pixel clock having frequency P at least substantially equal to (2/3)L in response to the link clock, and the receiver operating in the 12-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a third fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters a third blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a first blanking state, a second blanking state, and the third blanking state.

12. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the circuitry is configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data, and

wherein K=8, the receiver is operable in a 16-bit mode in which N=16, the sequence of 8-bit fragments is a sequence of groups, each said group consists of two of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 16-bit mode to generate a pixel clock having frequency P at least substantially equal to L/2 in response to the link clock, and the receiver operating in the 16-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a first fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters a first blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a second blanking state, and the first blanking state.

13. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the sequence of packed K-bit fragments is a sequence of groups of M fragments, where M=N/D, D is the greatest common divisor of N and K, and the subsystem in each said N-bit mode is configured to execute state sequences, each consisting of M states, during operation in each said N-bit mode, said state sequences including:

active video interval sequences, wherein M of the fragments are recovered during each of the active video interval sequences;

blanking interval sequences, wherein M blanking characters are recovered during each of the blanking interval sequences, and one of said M blanking characters is identical to another one of said M blanking characters;

active video to blanking transitional sequences, wherein one of the fragments is recovered during a first state of each of the active video to blanking transitional sequences and a blanking character is recovered during a last state of each of the active video to blanking transitional sequences; and

blanking to active video transitional sequences, wherein one of the fragments is recovered during a last state of each of the blanking to active video transitional sequences and a blanking character is recovered during a first state of each of the blanking to active video transitional sequences,

wherein the subsystem in each said N-bit mode is configured to recover the sequence of N-bit video data words by executing, completely or partially, a sufficient number of state sequence cycles, each of the state sequence cycles including any number of the active video interval sequences, followed by one of the active video to blanking transitional sequences, followed by a number of the blanking interval sequences, followed by one of the blanking to active video transitional sequences.

14. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the circuitry is also configured to generate a multiphase clock set in response to a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the multiphase clock set includes X clocks, each of said clocks having a different phase and a frequency at least substantially equal to Y*L, where X and Y are integers, so that the multiphase clock set defines X*Y subdivisions of each period of the link clock, and the circuitry includes a frequency divider coupled to receive at least one clock of the multiphase clock set and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the at least one clock of the multiphase clock set, wherein the frequency divider is configured to generate a waveform, to generate at least one phase shifted version of the waveform, and to combine the waveform and at least one said phase shifted version of the waveform to generate the pixel clock.

15. A receiver, including:

circuitry having inputs configured to be coupled to a transition minimized differential signaling (TMDS) link, wherein the circuitry is configured to configured to recover TMDS code words indicative of 8-bit words of video data that have been transmitted to at least a subset of the inputs and to decode the code words to recover the 8-bit words of video data; and

a subsystem coupled to the circuitry to receive sequences of the 8-bit words and operable in any selected one of a number of different 3N-bit pixel modes in which N≠8 and the sequences of the 8-bit words are sequences of packed 8-bit fragments of 3N-bit pixels, wherein the subsystem is operable in each said 3N-bit pixel mode to unpack the fragments to recover a sequence of the 3N-bit pixels, the 3N-bit pixel modes include a 30-bit pixel mode, a 36-bit pixel mode, and a 48-bit pixel mode, the receiver is also operable in a 24-bit pixel mode in which the sequences of the 8-bit words received by the subsystem are sequences of 24-bit pixels, and

the circuitry is also configured to recover a link clock having frequency L that has been transmitted to at least a subset of the inputs over the TMDS link, and the circuitry includes a frequency divider coupled to receive the link clock and operable in each said 3N-bit pixel mode to generate a pixel clock having frequency P at least substantially equal to (8/N)L in response to the link clock.

16. A system, including:

a transmitter;

a receiver; and

a serial link coupled between the transmitter and the receiver, wherein the transmitter comprises:

a subsystem operable in at least one N-bit mode to pack a sequence of N-bit words of video data into a sequence of fragments, where N≠K and each of the fragments consists of K bits of the video data; and

circuitry coupled to the subsystem and having outputs configured to be coupled to data channels of the serial link, wherein the circuitry is configured to generate a sequence of encoded fragments by encoding the fragments and to assert the sequence of encoded fragments to the outputs to transmit the encoded fragments to the receiver over the link, wherein the sequence of encoded fragments is a sequence of groups of the encoded fragments, each of the groups determines a different one of the N-bit words of video data, and the circuitry of the transmitter is configured to assert the groups sequentially to the outputs, and wherein the N-bit words of video data are asserted to the subsystem at a first rate equal to P of the N-bit words per unit time and the circuitry of the transmitter is configured to assert the sequence of encoded fragments to the outputs at a second rate that is at least substantially equal to (N/K)P of the encoded fragments per unit time, and wherein the receiver includes:

receiver circuitry having inputs coupled to the serial link and configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of inputs over the serial link and to decode the code words to recover the K-bit words of video data; and

an unpacking subsystem coupled to the receiver circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the unpacking subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words.

17. The system of claim 16 , wherein K=8, the link is a transition minimized differential signaling (TMDS) link, and the receiver circuitry is configured to recover 10-bit TMDS code words indicative of the 8-bit words of video data and to decode the TMDS code words to recover the 8-bit words of video data.

18. The system of claim 16 , wherein the receiver circuitry is also configured to generate a multiphase clock set in response to a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the multiphase clock set includes X clocks, each of said clocks having a different phase and a frequency at least substantially equal to Y*L, where X and Y are integers, so that the multiphase clock set defines X*Y subdivisions of each period of the link clock, and the receiver circuitry includes a frequency divider coupled to receive at least one clock of the multiphase clock set and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the at least one clock of the multiphase clock set, wherein the frequency divider is configured to generate a waveform, to generate at least one phase shifted version of the waveform, and to combine the waveform and at least one said phase shifted version of the waveform to generate the pixel clock.

19. The system of claim 16 , wherein the sequence of encoded fragments is a sequence of groups of the encoded fragments, each of the groups determines a different one of the N-bit words of video data, and the circuitry of the transmitter is configured to assert the groups sequentially to the outputs, and wherein the N-bit words of video data are asserted to the subsystem at a first rate equal to P of the N-bit words per unit time and the circuitry of the transmitter is configured to assert the sequence of encoded fragments to the outputs at a second rate that is at least substantially equal to (N/K)P of the encoded fragments per unit time.

20. The system of claim 19 , wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, where M=N/D, and D is the greatest common divisor of N and K.

21. A system, including:

a transmitter;

a receiver; and

a serial link coupled between the transmitter and the receiver, wherein the transmitter comprises:

a subsystem operable in at least one N-bit mode to pack a sequence of N-bit words of video data into a sequence of fragments, where N≠K and each of the fragments consists of K bits of the video data;

circuitry coupled to the subsystem and having outputs configured to be coupled to data channels of the serial link, wherein the circuitry is configured to generate a sequence of encoded fragments by encoding the fragments and to assert the sequence of encoded fragments to the outputs to transmit the encoded fragments to the receiver over the link; and

a video source coupled to the transmitter and configured to assert the N-bit words of video data and a pixel clock having frequency P to the transmitter, wherein the transmitter is also operable in each said N-bit mode to assert the sequence of encoded fragments to the outputs during active video intervals at a rate of one encoded fragment per cycle of a link clock having frequency L at least substantially equal to (N/K)P, and the transmitter is also operable in each said N-bit mode to transmit the link clock over a clock channel of the link.

22. The system of claim 21 , wherein the receiver includes:

receiver circuitry having inputs coupled to the serial link and configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data; and

an unpacking subsystem coupled to the receiver circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the unpacking subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, and

wherein the receiver circuitry is also coupled to the clock channel of the link and configured to recover the link clock that has been transmitted over the clock channel, and the receiver circuitry includes a frequency divider coupled to receive the link clock and operable in each said N-bit mode to generate a pixel clock having frequency P substantially equal to (K/N)L in response to the link clock.

23. The system of claim 22 , wherein the unpacking subsystem includes a FIFO coupled to receive the link clock and the pixel clock, and the unpacking subsystem is configured to clock the fragments into the FIFO in response to the link clock and to clock the sequence N-bit video data words out of the FIFO in response to the pixel clock.

24. The system of claim 21 , wherein the sequence of encoded fragments is a sequence of groups of the encoded fragments, each of the groups determines a different one of the N-bit words of video data, and the circuitry of the transmitter is configured to assert the groups sequentially to the outputs, and wherein the N-bit words of video data are asserted to the subsystem at a first rate equal to P of the N-bit words per unit time and the circuitry of the transmitter is configured to assert the sequence of encoded fragments to the outputs at a second rate that is at least substantially equal to (N/K)P of the encoded fragments per unit time.

25. The system of claim 24 , wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, where M=N/D, and D is the greatest common divisor of N and K.