Time base correction and frame rate conversion

1. An apparatus comprising:

circuitry to synthesize an output video clock;

circuitry to receive an input video synchronization signal;

circuitry to change a frequency of the output video clock based on an intended number of video output clock cycles per input vertical period and a period of the input video synchronization signal;

wherein the circuitry to change a frequency of the output video clock comprises:

circuitry to generate an error signal based on a comparison of the intended number of video output clock cycles per input vertical period and an actual number of video output clock cycles per input vertical period, wherein the period of the input video synchronization signal determines a length of the input vertical period;

circuitry that receives the error signal and generates a frequency signal;

wherein the circuitry to generate an error signal comprises a counter;

wherein the circuitry that receives the error signal and generates a frequency signal comprises one or more of, multiplication circuitry, a serial generator, a trigger generator having an output coupled to the serial generator, and an accumulator;

wherein the accumulator comprises:

addition circuitry and

a latch.

2. The apparatus of claim 1 ,

wherein the circuitry to synthesize an output video clock comprises direct digital synthesis circuitry.

3. The apparatus of claim 1 , wherein the circuitry to receive an input video synchronization signal comprises a trigger generator.

4. The apparatus of claim 1 , wherein the output video clock is an output video pixel clock.

5. The apparatus of claim 1 , wherein the input video synchronization signal is an input video vertical synchronization signal.

6. The apparatus of claim 1 , wherein the input vertical period is one or more of an input frame and an input field.

7. A method for time base correction, comprising:

comparing on an input vertical period by input vertical period basis an intended number of output clock cycles per input vertical period with an actual number of output clock cycles per input vertical period and generating an error number based on the comparison, wherein the error number can be positive, negative, or zero;

using the error number to generate a frequency tuning number;

synthesizing an output video clock based on the frequency tuning number;

wherein comparing on an input vertical period by input vertical period basis an intended number of output clock cycles per input vertical period with an actual number of output clock cycles per input vertical period comprises:

using an input video synchronization signal to control a loading of a counter with the intended number of output clock cycles per input vertical period;

using an existing output video clock to decrement the counter;

using a resulting output of the counter as the error number.

8. The method of claim 7 , wherein the input video synchronization signal is an input video vertical synchronization signal.

9. A method for time base correction, comprising:

comparing on an input vertical period by input vertical period basis an intended number of output clock cycles per input vertical period with an actual number of output clock cycles per input vertical period and generating an error number based on the comparison, wherein the error number can be positive, negative, or zero;

using the error number to generate a frequency tuning number;

synthesizing an output video clock based on the frequency tuning number;

wherein using the error number to generate a frequency tuning number comprises:

multiplying the error number to generate a frequency error number;

adding the frequency error number to a latched frequency sum number to get a frequency sum;

latching the frequency sum as a new latched frequency sum number; and

using the latched frequency sum number as the frequency tuning number.

10. The method of claim 9 , wherein the multiplying is by a number that equals an integer power of two and involves a binary left shift.

11. A method for frame rate conversion, comprising:

calculating an intended number of output clock cycles per input vertical period by dividing an intended output vertical synchronization frequency by an input vertical synchronization frequency and multiplying the result by an intended number of video output clock cycles per output vertical period;

comparing on an input vertical period by input vertical period basis the intended number of output clock cycles per input vertical period with an actual number of output clock cycles per input vertical period and generating an error number based on the comparison, wherein the error number can be positive, negative, or zero;

using the error number to generate a frequency tuning number;

synthesizing an output video clock based on the frequency tuning number.

12. The method of claim 11 , wherein a period of an input video synchronization signal determines a length of the input vertical period.

13. The method of claim 11 , wherein comparing on an input vertical period by input vertical period basis an intended number of output clock cycles per input frame with an actual number of output clock cycles per input frame comprises:

using an input video synchronization signal to control a loading of a counter with the intended number of output clock cycles per input frame;

using an existing output video clock to decrement the counter;

using a resulting output of the counter as the error number.

14. The method of claim 13 , wherein the input video synchronization signal is an input video vertical synchronization signal.

15. The method of claim 11 , wherein using the error number to generate a frequency tuning number comprises:

multiplying the error number to generate a frequency error number;

adding the frequency error number to a latched frequency sum number to get a frequency sum;

latching the frequency sum as a new latched frequency sum number; and

using the latched frequency sum number as the frequency tuning number.

16. The method of claim 15 , wherein the multiplying is by a number that equals an integer power of two and involves a binary left shift.

17. The method of claim 11 , wherein the vertical period is one or more of a frame and a field.

18. The method of claim 11 , wherein the intended output vertical synchronization frequency is one of 72 Hertz, 48 Hertz, or 24 Hertz, and the input vertical synchronization frequency is 60 Hertz.