Method and apparatus for deinterlacing digital video images
View Patent ↗A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to perform frequency analysis upon the received interlaced video stream in order to generate the deinterlaced video stream having reduced motion artifacts.
1. A digital image processor comprising:
a digital processing unit;
an input operable to receive an interlaced video stream;
a digital memory unit for storing portions of the interlaced video signal;
an output operable to transmit a deinterlaced video stream;
a deinterlacing processor implemented upon said digital processing unit, said deinterlacing processor coupled to said input, said output, and said digital memory unit, said deinterlacing processor operable to perform frequency analysis upon said received interlaced video stream in order to generate said deinterlaced video stream having reduced motion artifacts;
wherein the deinterlacing processor performs frequency analysis upon a plurality of vertically aligned pixels of a video frame, said video frame including two adjacent video fields to detect a motion artifact;
wherein a frequency being analyzed is a spatial frequency;
wherein the deinterlacing uses the results of the frequency analysis to reduce the visibility of the motion artifact in the video frame and wherein the deinterlacing processor determines a plurality of motion artifact detection values from the motion artifact; and
wherein the deinterlacing processor determines an ultimate detection value for each of the plurality of motion artifact detection values wherein the ultimate detection value is based upon a predetermined digital that has a spatial frequency of 0.5 cycles/line and a number of elements equal to the plurality of vertically aligned pixels.
2. A digital image processor as recited in claim 1 , wherein the deinterlacing processor mixes each of the plurality of pixels with a set of interpolated spatially corresponding pixels, while using the ultimate detection value as a control, to generate an output pixel for each of the plurality of pixels.
3. A digital image processor as recited in claim 1 , wherein the deinterlacing processor determines a second video frame from the input of the interlaced video stream, the second video frame including pixels that spatially correspond to pixels of said first video frame.
4. A digital image processor as recited in claim 1 , wherein the plurality of motion artifact detection values has a magnitude that is proportional to an intensity of the detected motion artifact.