IP Library Granted Patent US 9,628,855
Granted Patent B2
US 9,628,855 · App. 14/620,973 · Granted Apr 18, 2017

Secure internal control for encrypting video data

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,628,855
App. No.
14/620,973
Granted
Apr 18, 2017
Kind
B2
Abstract

In one aspect, a video processing device includes a processor and a transmitter, for example implemented as separate integrated circuits on a printed circuit board. Pins on the processor are coupled to pins on the transmitter via a data channel, for example conductive leads on the printed circuit board. Video data is transmitted from the processor to the transmitter via this data channel, which is high speed enough to accommodate video data. The transmitter also includes an encryption engine used to encrypt the video data. Encryption control data, which determines the encryption to be applied, is transmitted from the processor to the transmitter over the same data channel as the video data. This is more secure than transmitting the encryption control data over a slower separate data channel, because the high speed video channel is harder to tamper with.

Claims (44)

1. A transmitter for encrypting and transmitting video data, comprising:

a data receive interface having data receive pin(s), the data receive interface receiving unencrypted video data and encryption control data via the data receive pin(s) from a first data channel;

an encryption engine coupled to the data receive interface, the encryption engine encrypting the unencrypted video data in accordance with the encryption control data;

a data output interface coupled to the encryption engine, the data output interface having data output pin(s) and transmitting the encrypted video data via the data output pin(s) to a second data channel; and

a control interface having control pin(s), the control interface receiving control signals via the control pin(s) from a side channel that is separate from and lower speed than the first data channel, the control signals controlling operation of the transmitter.

2. The transmitter of claim 1 , wherein the encryption control data specifies a level of encryption applied by the encryption engine.

3. The transmitter of claim 2 , wherein the encryption engine comprises a register that stores the level of encryption to be applied by the encryption engine.

4. The transmitter of claim 1 , wherein the encryption control data specifies whether or not to apply encryption.

5. The transmitter of claim 1 , wherein:

the data output interface transmits the encrypted video data to an external device via the second data channel;

the encryption control data specifies a minimum level of encryption applied by the encryption engine;

the transmitter determines whether the external device supports the minimum level of encryption; and

if the external device does not support the minimum level of encryption, the transmitter does not transmit data over the second data channel.

6. The transmitter of claim 1 , wherein:

the encryption control data includes lock/unlock instructions that place the encryption engine into a lock state or into an unlock state;

in a lock state, a level of encryption applied by the encryption engine cannot be changed by data received via the side channel; and

in an unlock state, the level of encryption applied by the encryption engine can be changed by data received via the side channel.

7. The transmitter of claim 6 , wherein the encryption engine automatically changes from a lock state to an unlock state, if no lock/unlock instruction to place or keep the encryption engine in the lock state is received during a predetermined timeout period.

8. The transmitter of claim 1 , wherein the first data channel is at least 1000 times higher data rate than the side channel.

9. The transmitter of claim 1 , wherein the side channel is a shared bus and the first data channel is a point-to-point link.

10. The transmitter of claim 1 , wherein the control interface further transmits status signals via the control pin(s) to the side channel.

11. The transmitter of claim 10 , wherein:

the data output interface transmits the encrypted video data to an external device via the second data channel;

the encryption control data specifies a level of encryption applied by the encryption engine;

the transmitter determines whether the external device supports the specified level of encryption; and

the status signal transmitted via the side channel indicates whether the external device supports the specified level of encryption.

12. The transmitter of claim 1 , wherein the data output interface transmits data in compliance with the HDMI, MHL or DisplayPort standards, and the encryption engine is an HDCP encryption engine.

13. A processor, comprising:

a data transmit interface having data transmit pins, the data transmit interface transmitting unencrypted video data and encryption control data via the data transmit pin(s) to a first data channel, the encryption control data determining encryption to be applied by an encryption engine to the unencrypted video data; and

a control interface having control pins, the control interface transmitting control signals via the control pin(s) to a side channel that is separate from and lower speed than the first data channel, the control signals controlling operation of a transmitter that transmits the video data encrypted by the encryption engine.

14. A device comprising:

a processor comprising a data transmit interface having data transmit pin(s), and a control transmit interface having control transmit pin(s);

a transmitter comprising a data receive interface having data receive pin(s), and a control receive interface having control receive pin(s);

a first data channel coupled on one end via the data transmit pin(s) to the data transmit interface, and on the other end via the data receive pin(s) to the data receive interface, the first data channel transporting unencrypted video data and encryption control data from the processor to the transmitter;

a side channel coupled on one end via the control transmit pin(s) to the control transmit interface, and on the other end via the control receive pin(s) to the control receive interface, the side channel separate from and lower speed than the first data channel, the control signals controlling operation of the transmitter;

the transmitter further comprising:

an encryption engine coupled to the data receive interface, the encryption engine encrypting the unencrypted video data in accordance with the encryption control data; and

a data output interface coupled to the encryption engine, the data output interface having an external connector and transmitting the encrypted video data via the external connector to a second data channel.

15. The device of claim 14 , wherein the processor and transmitter are implemented as separate integrated circuits, and the first data channel includes conducting leads connecting the data transmit pins and the data receive pins of the separate integrated circuits.

16. The device of claim 14 , wherein, in the transmitter, the encryption engine is implemented as an integrated circuit that does not contain the data receive interface or the data output interface.

17. The device of claim 14 , wherein the external connector is a mechanical connector.

18. The device of claim 14 , wherein the external connector is a wireless connector.

19. The device of claim 14 , wherein the data output interface transmits the encrypted video data via the second data channel to an external display device.

20. The device of claim 14 , wherein the data output interface transmits data in compliance with the HDMI, MHL or DisplayPort standards, and the encryption engine is an HDCP encryption engine.

Assignments (4)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
SECURITY INTEREST Recorded Mar 8, 2016
From: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 037924/0839 →
MERGER Recorded Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2015
From: CHOI, HOON; YANG, WOOSEUNG; YI, JU HWAN
To: SILICON IMAGE, INC.
Reel/Frame 034952/0565 →