Mechanism for low power standby mode control circuit
View Patent ↗Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
1. An apparatus comprising:
a processor;
an interface for a cable connection with a second apparatus;
a detection element to detect the cable connection with the second apparatus at the interface;
an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode; and
a standby mode control circuit, the standby mode control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby mode control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit,
wherein the stimulus signal is received from the second apparatus via a control bus (CBUS) in connection with the detection element detecting the cable connection with the second apparatus, the CBUS coupled to the operational circuit.
2. The apparatus of claim 1 , wherein the operational circuit is a receiver chip.
3. The apparatus of claim 1 , wherein the apparatus is a Mobile High-Definition Link (MHL) compatible device.
4. The apparatus of claim 1 , wherein the operational circuit includes a plurality of transistor element, the transistor elements being disabled when the one or more power connections are disabled.
5. The apparatus of claim 1 , wherein the operational circuit is to be placed in a power down state in the standby mode.
6. The apparatus of claim 1 , further comprising a first switch to couple the CBUS with the operational circuit and to turn on in response to the detection element detecting the cable connection with the second apparatus.
7. The apparatus of claim 1 , wherein the stimulus signal is a voltage level change on the CBUS.
8. A method comprising:
transitioning an apparatus or system to a standby mode;
disabling by a processor one or more power connections to an operational circuit;
operating a standby mode control circuit on a standby power source;
detecting by a detection element a cable connection with a second apparatus or system;
receiving a stimulus signal from the second apparatus or system at the standby mode control circuit; and
in response to the stimulus signal, generating a signal from the standby mode control circuit to the processor, the processor to enable the one more power connections in response to the signal from the standby mode control circuit,
wherein the stimulus signal is received from the second apparatus or system via a control bus (CBUS) in connection with the detection element detecting the cable connection with the second apparatus or system, the CBUS coupled to the operational circuit.
9. The method of claim 8 , wherein disabling the one or more power connections places the operational circuit in a power off mode.
10. The method of claim 8 , further comprising reducing leakage current consumption of the apparatus or system by disabling a plurality of transistors of the operational circuit in the standby mode.
11. The method of claim 8 , wherein the operational circuit is a receiver chip.
12. The method of claim 8 , wherein the apparatus or system is a Mobile High-Definition Link (MHL) compatible apparatus or system.
13. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
transitioning an apparatus or system to a standby mode;
disabling by a processor one or more power connections to an operational circuit;
operating a standby mode control circuit on a standby power source;
detecting by a detection element a cable connection with a second apparatus or system;
receiving a stimulus signal from the second apparatus or system at the standby mode control circuit; and
in response to the stimulus signal, generating a signal from the standby mode control circuit to the processor, the processor to enable the one more power connections in response to the signal from the standby mode control circuit,
wherein the stimulus signal is received the second apparatus or system via a control bus (CBUS) in connection with the detection element detecting the cable connection with the second apparatus or system, the CBUS coupled to the operational circuit.
14. The medium of claim 13 , wherein disabling the one or more power connections places the operational circuit in a power off mode.
15. The medium of claim 13 , further comprising instructions that, when executed by the processor, cause the processor to perform operations comprising:
reducing leakage current consumption of the apparatus or system by disabling a plurality of transistors of the operational circuit in the standby mode.
16. The medium of claim 13 , wherein the operational circuit is a receiver chip.
17. The medium of claim 13 , wherein the apparatus or system is a Mobile High-Definition Link (MHL) compatible apparatus or system.