Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices
View Patent ↗A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.
1. An apparatus comprising:
a plurality of memory cells including a plurality of data cells, a first supplemental cell and a second supplemental cell; and
a refresh logic coupled to the plurality of memory cells, the refresh logic configured to:
calibrate a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by:
sampling a data cell of the plurality of data cells, the first supplemental cell, and the second supplemental cell,
calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and
calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell, and
refresh the plurality of data cells at the first refresh rate,
refresh the first supplemental cell at the second refresh rate,
refresh the second supplemental cell at the third refresh rate,
increase the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level, and
decrease the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermined level.
2. The apparatus of claim 1 , wherein the memory device comprises a Dynamic Random Access Memory (DRAM) device.
3. The apparatus of claim 1 , wherein the supplemental cells are further configured to store data responsive to one of the plurality of data cells being faulty.
4. The apparatus of claim 1 , wherein the first and second supplemental cells are refreshed by storing the second value.
5. The apparatus of claim 1 , wherein the first value is a logical low value, and wherein the second value is a logical high value.
6. The apparatus of claim 1 , wherein each of the second refresh rate and the third refresh rate is an integer fraction of the first refresh rate.
7. The apparatus of claim 6 , wherein the second refresh rate is twice the third refresh rate.
8. The apparatus of claim 1 , wherein the first and second supplemental cells are distributed in columns of the plurality of memory cells.
9. The apparatus of claim 1 , wherein the refresh logic is further configured to calibrate the first refresh, the second refresh rate and the third refresh rate during an initialization stage of the apparatus.
10. A system comprising:
a processor; and
a memory device comprising:
a plurality of memory cells including a plurality of data cells, a first supplemental cell a second supplemental cell; and
a refresh logic coupled to the plurality of memory cells, the refresh logic configured to:
calibrate a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by:
sampling a data cell of the plurality of data cells, the first supplemental cell, and the second supplemental cell,
calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and
calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell,
refresh the plurality of data cells at a first refresh rate,
refresh the first supplemental cell at a second refresh rate slower than the first refresh rate,
refresh the second supplemental cell at a third rate slower than the first refresh rate and the second refresh rate,
increase the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level, and
decrease the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermined level.
11. The system of claim 10 , wherein the memory device comprises a Dynamic Random Access Memory (DRAM) device.
12. The system of claim 10 , wherein the supplemental cells are further configured to store data responsive to one of the plurality of data cells being faulty.
13. The system of claim 10 , wherein the first and second supplemental cells are refreshed by storing the second value.
14. The system of claim 10 , wherein the first value is a logical low value, and wherein the second value is a logical high value.
15. The system of claim 10 , wherein each of the second refresh rate and the third refresh rate is an integer fraction of the first refresh rate.
16. The system of claim 15 , wherein the second refresh rate is twice the third refresh rate.
17. The system of claim 10 , wherein the first and second supplemental cells are distributed in columns of the plurality of memory cells.
18. The system of claim 10 , wherein the refresh logic is further configured to calibrate the first refresh, the second refresh rate and the third refresh rate during an initialization stage of the apparatus.
19. A method comprising:
calibrating a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by:
sampling a data cell of the plurality of data cell, the first supplemental cell, and the second supplemental cell,
calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and
calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell;
refreshing the plurality of data cells at a first refresh rate;
refreshing a first supplemental cell at a second refresh rate slower than the first refresh rate;
refreshing a second supplemental cell at a third rate slower than the first refresh rate and the second refresh rate;
increasing the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level; and
decreasing the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermine level.
20. The method of claim 19 , wherein the first and second supplemental cells are refreshed by storing the second value, wherein the first value is a logical low value, and wherein the second value is a logical high value.
21. The method of claim 19 , wherein each of the second refresh rate and the third refresh rate is an integer fraction of the first refresh rate.
22. The method of claim 19 , wherein the second refresh rate is twice the third refresh rate.
23. The method of claim 19 , further comprising calibrating the first refresh rate, the second refresh rate and the third refresh rate during an initialization stage of the plurality of memory cells.