Configuration sequence for programmable logic device
View Patent ↗Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.
1. A method comprising:
programming a first portion of a programmable logic device (PLD) with first configuration data, wherein the first portion comprises a physical coding sublayer (PCS) block and an intellectual property core (IP) block, wherein the programming the first portion comprises:
configuring the PCS block with at least a first subset of the first configuration data; and
passing at least a second subset of the first configuration data from the PCS block to the IP block; and
after the first portion is programmed, operating the IP block in accordance with a communication standard to exchange data with a host system while programming a second portion of the PLD with second configuration data.
2. The method of claim 1 , further comprising:
synchronizing the programming of the first portion by a first clock signal; and
synchronizing the operating of the IP block by a second clock signal while synchronizing the programming of the second portion by the first clock signal.
3. The method of claim 2 , wherein the PLD is implemented in a subsystem of the host system, the method further comprising:
generating the first clock signal at the subsystem; and
receiving the second clock signal at the subsystem from the host system.
4. The method of claim 1 , wherein:
the host system is a computer system;
the PLD is implemented in a peripheral component interconnect express (PCIe) subsystem of the computer system;
the communication standard is a PCIe standard; and
the first portion is programmed in less than 100 ms to comply with the PCIe standard.
5. The method of claim 4 , wherein the PCIe subsystem is a peripheral card installed in a motherboard of the computer system.
6. The method of claim 1 , further comprising disabling a data path between the first and second portions while the second portion is programmed.
7. The method of claim 1 , wherein the IP block is a configurable hard IP block.
8. The method of claim 1 , wherein the IP block is a non-configurable hard IP block, wherein the non-configurable hard IP block is not programmed with the first configuration data.
9. A device comprising:
a first portion of a programmable logic device (PLD) adapted to be programmed with first configuration data, wherein the first portion comprises:
an intellectual property core (IP) block; and
a physical coding sublayer (PCS) block adapted to be programmed by at least a first subset of the first configuration data and pass at least a second subset of the first configuration data from the PCS block to the IP block;
a second portion of the PLD adapted to be programmed with second configuration data; and
wherein the IP block is adapted to operate in accordance with a communication standard to exchange data with a host system after the first portion is programmed and while the second portion is programmed.
10. The device of claim 9 , wherein:
the first portion is adapted to synchronize to a first clock signal while the first portion is programmed and to a second clock signal while the second portion is programmed; and
the second portion is adapted to synchronize to the first clock signal while the second portion is programmed.
11. The device of claim 10 , further comprising a subsystem of the host system, the subsystem comprising:
the PLD;
a clock generator adapted to generate the first clock signal; and
wherein the second clock signal is received at the subsystem from the host system.
12. The device of claim 9 , wherein:
the host system is a computer system;
the PLD is part of a peripheral component interconnect express (PCIe) subsystem adapted to be implemented in the computer system;
the communication standard is a PCIe standard; and
the first portion is adapted to be programmed in less than 100 ms to comply with the PCIe standard.
13. The device of claim 12 , wherein the PCIe subsystem is a peripheral card adapted to be installed in a motherboard of the computer system.
14. The device of claim 9 , wherein the first portion is adapted to disable a data path between the first and second portions while the second portion is programmed.
15. The device of claim 9 , wherein the IP block is a configurable hard IP block.
16. The device of claim 9 , wherein:
the IP block is a non-configurable hard IP block; and
the non-configurable hard IP block is not programmed with the first configuration data.