Patent Assignment
Reel/Frame 035309/0142
Security Interest
Recorded: 2015-03-24
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(93)
High Speed First-in-First-Out Memory
Patent:
4,642,797 →
Application:
06/551,735 →
Programmable Logic Device with Limited Sense Currents and Noise Isolation
Patent:
4,833,646 →
Application:
06/707,670 →
In-System Programmable Logic Device
Patent:
4,879,688 →
Application:
06/862,815 →
Programmable Logic Array
Patent:
4,766,569 →
Application:
06/871,063 →
One-Time Programmable Data Security System for Programmable Logic Device
Patent:
4,887,239 →
Application:
06/882,602 →
Programmable Data Security Circuit for Programmable Logic Device
Patent:
4,852,044 →
Application:
07/236,348 →
Programmable Logic Device Configurable Input/Output Cell
Patent:
4,896,296 →
Application:
07/288,945 →
Interconnect Structure for Programmable Logic Device
Patent:
5,255,203 →
Application:
07/538,211 →
Fully Configurable Versatile Field Programmable Function Element
Patent:
5,255,221 →
Application:
07/679,370 →
Non-Volatile Erasable and Programmable Interconnect Cell
Patent:
5,251,169 →
Application:
07/696,453 →
Tunable Voltage Reference Circuit to Provide an Output Voltage with a Predetermined Temperature Coefficient Independent of Variation in Supply Voltage
Patent:
5,281,906 →
Application:
07/785,442 →
Temperature Compensated Cmos Voltage to Current Converter
Patent:
5,231,316 →
Application:
07/853,453 →
Active Clamp Circuit Scheme for Cmos Devices
Patent:
5,357,156 →
Application:
07/911,841 →
Arrangement for Parallel Programming of in-System Programmable Ic Logic Devices
Patent:
5,329,179 →
Application:
07/957,311 →
Programmable Integrated-Circuit Switch
Patent:
5,452,229 →
Application:
07/993,711 →
Single Polysilicon Layer E2PROM Cell
Patent:
5,418,390 →
Application:
08/033,934 →
Sense Amplifiers and Sensing Methods
Patent:
5,394,037 →
Application:
08/042,533 →
Multiplexed Control Pins for in-System Programming and Boundary Scan State Machines in a High Density Programmable Logic Device
Patent:
5,412,260 →
Application:
08/106,263 →
Programmable Semiconductor Antifuse Structure and Method of Fabricating
Patent:
5,353,246 →
Application:
08/108,363 →
Input Routing Pool
Patent:
5,404,055 →
Application:
08/115,533 →
Structure and Method for Implementing Hierarchical Routing Pools in a Programmable Logic Circuit
Patent:
5,394,033 →
Application:
08/115,723 →
Single Polysilicon Layer Flash E2PROM Cell
Patent:
5,886,378 →
Application:
08/179,887 →
Output Enable Structure and Method for a Programmable Logic Device
Patent:
5,506,517 →
Application:
08/342,675 →
Inkjet Printer, Drive Method and Drive Device for Same
Programmable Logic Function Generator Using Non-Volatile Programmable Memory Switches
Serdes with Programmable I/O Architecture
Patent:
7,327,160 →
Application:
11/676,196 →
Receiver and Transmitter Calibration to Compensate for Frequency Dependent I/Q Imbalance
Patent:
7,856,050 →
Application:
11/839,107 →
Interface Block Architectures
Patent:
7,427,874 →
Application:
11/949,454 →
Method and System for Placing Integrated Circuits into Predominantly Ultra-Low Voltage Mode for Standby Purposes
Patent:
8,314,632 →
Application:
13/193,984 →
Dual-Port Sram with Bit Line Clamping
Patent:
8,451,679 →
Application:
13/212,121 →
Comparator with Jitter Mitigation
Patent:
8,169,237 →
Application:
13/275,102 →
Testing of Soft Error Detection Logic for Programmable Logic Devices
Patent:
8,370,691 →
Application:
13/299,507 →
Programmable Logic Device Data Rate Booster for Digital Signal Processing
Patent:
8,977,885 →
Application:
13/412,408 →
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,823,561 →
Application:
13/452,060 →
Low-Power Configurable Delay Element
Patent:
8,461,894 →
Application:
13/585,142 →
Serializer with Multiple Stages
Patent:
8,912,933 →
Application:
13/616,173 →
Triple-Trim Reference Voltage Generator
Patent:
8,710,898 →
Application:
13/653,827 →
Placing Integrated Circuits into Low Voltage Mode for Standby Purposes
Patent:
8,643,398 →
Application:
13/680,947 →
Multi-Channel Transmitter Synchronization Circuitry
Patent:
9,819,478 →
Application:
13/681,782 →
Integrated Circuit Package with Input Capacitance Compensation
Patent:
8,643,168 →
Application:
13/685,385 →
In-System Margin Measurement Circuit
Patent:
8,686,773 →
Application:
13/721,867 →
Hybrid H-Bridge and Cml Driver
Patent:
8,797,064 →
Application:
13/738,265 →
Programmable Signal Routing Systems Having Low Static Leakage
Patent:
45,200 →
Application:
13/764,221 →
Leakage-Current Abatement Circuitry for Memory Arrays
Integrated Circuit with Pin for Setting Digital Address
Patent:
8,786,482 →
Application:
13/857,919 →
Highly Secure and Extensive Scan Testing of Integrated Circuits
Loss of Signal Detection for High-Speed Serial Links
Delaying Data Signals
Dual-Port Sram with Bit Line Clamping
Configuration Sequence for Programmable Logic Device
Stable Supply-Side Reference Over Extended Voltage Range With Hot-Plugging Compatibility
Phase Locked Loop Circuit with Selectable Feedback Paths
Application:
14/021,513 →
Publication:
US 2014/0009194
Dynamic Power Supply Switching for Clocking Signals
Patent:
8,829,944 →
Application:
14/040,955 →
Serdes Interface Architecture for Multi-Processor Systems
Configuration of Selected Modules of a Hardware Block Within a Programmable Logic Device
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Esd Protection Using Shared Rc Trigger
Clock Assignments for Programmable Logic Device
Application:
14/136,482 →
Publication:
US 2015/0178436
Group Based Routing in Programmable Logic Device
Hot-Socket Circuitry
Collector Current Driver for a Bipolar Junction Transistor Temperature Transducer
Low-Voltage Current Sense Amplifer
Component Placement with Repacking for Programmable Logic Devices
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Patent:
9,009,379 →
Application:
14/223,096 →
Transistor Matching for Generation of Precise Current Ratios
Semiconductor Defect Characterization
Partition Based Design Implementation for Programmable Logic Devices
Embedded Memory Testing Using Back-To-Back Write/Read Operations
PVT Compensation Scheme for Output Buffers
Trigger Detection for Post Configuration Testing of Programmable Logic Devices
Application:
14/313,443 →
Publication:
US 2015/0370672
Holdtime Correction Using Input/Output Block Delay
Efficient Constant Multiplier Implementation for Programmable Logic Devices
Incrementer Absorption into Multiplier Logic for Programmable Logic Devices
Patent:
9,152,753 →
Application:
14/319,481 →
Sram with Two-Level Voltage Regulator
Mixed-Width Memory Techniques for Programmable Logic Devices
System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability
Clock to Out Path Optimization
Application:
14/339,164 →
Publication:
US 2016/0026745
Bus-Based Clock to Out Path Optimization
Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing
Application:
14/482,001 →
Publication:
US 2015/0310933
Logic Absorption Techniques for Programmable Logic Devices
Level Shifter With Low Static Power Dissipation
Application:
14/525,240 →
Publication:
US 2016/0118987
Meta-Stability Prevention for Oscillators
Application:
14/535,351 →
Publication:
US 2016/0134264
Class Ab Amplifier with Programmable Quiescent Current
Programmable Filter
Patent:
9,325,302 →
Application:
14/558,851 →
Sharing a Common Resource Via Multiple Interfaces
Application:
14/576,245 →
Publication:
US 2016/0179707
Reconfigurable and Scalable Hardware Management Architecture
Registers for Post Configuration Testing of Programmable Logic Devices
Hotswap Operations for Programmable Logic Devices
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Multiple Mode Device Implementation for Programmable Logic Devices
High Speed Complementary Nmos Lut Logic
Shared Logic for Multiple Registers with Asynchronous Initialization
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 6, 2015
From: LATTICE SEMICONDUCTOR LIMITED
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 035101/0559 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →