Multi-channel transmitter synchronization circuitry
View Patent ↗In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.
1. An integrated circuit comprising:
a first multi-channel transmitter having synchronization (sync) circuitry comprising:
a first sync stage configured to synchronize a reset signal to a local clock signal to generate a first-synchronized reset signal; and
a second sync stage configured to synchronize each of a plurality of copies of the first-synchronized reset signal to the local clock signal to generate a plurality of second-synchronized reset signals, where each second-synchronized reset signal is applied to reset a different transmit channel of the first multi-channel transmitter,
wherein the first multi-channel transmitter is configured to select the local clock signal, against which the reset signal is to be synchronized, from any one of a plurality of available clock signals.
2. The invention of claim 1 , wherein:
the first sync stage comprises a first-stage sync cell configured to receive the reset signal and the local clock signal and generate the first-synchronized reset signal; and
the second sync stage comprises a different second-stage sync cell for each different transmit channel, each different sync cell configured to receive a corresponding copy of the first-synchronized reset signal and the local clock signal and generate one of the second-synchronized reset signals.
3. The invention of claim 2 , wherein the first-stage sync cell comprises:
a first set of one or more buffers connected in series to receive the reset signal and generate a buffered reset signal;
a second set of one or more buffers connected in series to receive the local clock signal and generate a buffered local clock signal;
a first flip-flop connected to receive the buffered reset signal and the buffered local clock signal and generate a latched reset signal; and
a second flip-flop connected to receive the latched reset signal and the buffered local clock signal and generate the first-synchronized reset signal.
4. The invention of claim 2 , wherein each second-stage sync cell comprises:
a first set of one or more buffers connected in series to receive the corresponding copy of the first-synchronized reset signal and generate a buffered first-synchronized reset signal;
a second set of one or more buffers connected in series to receive the local clock signal and generate a buffered local clock signal;
a first flip-flop connected to receive the buffered first-synchronized reset signal and the buffered local clock signal and generate a latched first-synchronized reset signal; and
a second flip-flop connected to receive the latched first-synchronized reset signal and the buffered local clock signal and generate the corresponding one of the second-synchronized reset signals.
5. The invention of claim 1 , wherein:
the first multi-channel transmitter is configured to generate a first set of transmit signals; and
the integrated circuit further comprises a second multi-channel transmitter configured to generate a second set of transmit signals, wherein the first and second multi-channel transmitters can be configured to use a common clock signal to generate the first and second sets of transmit signals.
6. The invention of claim 5 , wherein each multi-channel transmitter can be configured to select any one of a plurality of available clock signals as its local clock signal, wherein one of the available clock signals is a neighbor clock signal corresponding to the clock signal selected by the other multi-channel transmitter as its local clock signal.
7. The invention of claim 1 , wherein the integrated circuit comprises:
a first quad having the first multi-channel transmitter configured to generate a first set of four transmit signals; and
a second quad having a second multi-channel transmitter configured to generate a second set of four transmit signals, wherein the first and second quads can be configured to use a common clock signal to generate the first and second sets of transmit signals.
8. The invention of claim 7 , wherein each quad can be configured to select any one of a plurality of available clock signals as its local clock signal, wherein one of the available clock signals is a neighboring-quad clock signal corresponding to the clock signal selected by the other quad as its local clock signal.
9. An integrated circuit comprising: a first multi-channel transmitter having synchronization (sync) circuitry comprising:
a first sync stage configured to synchronize a reset signal to a local clock signal to generate a first-synchronized reset signal and
a second sync stage configured to synchronize each of a plurality of copies of the first-synchronized reset signal to the local clock signal to generate a plurality of second-synchronized reset signals, where each second-synchronized reset signal is applied to reset a different transmit channel of the first multi-channel transmitter,
wherein the first multi-channel transmitter is configured to select the local clock signal from any one of a plurality of available clock signals; and
wherein the first sync stage comprises a different first-stage sync cell for each available clock signal, wherein each different first-stage sync cell is configured to receive the reset signal and the corresponding available clock signal and generate a corresponding version of the first-synchronized reset signal.
10. An integrated circuit comprising: a first multi-channel transmitter having synchronization (sync) circuitry comprising:
a first sync stage configured to synchronize a reset signal to a local clock signal to generate a first-synchronized reset signal and
a second sync stage configured to synchronize each of a plurality of copies of the first-synchronized reset signal to the local clock signal to generate a plurality of second-synchronized reset signals, where each second-synchronized reset signal is applied to reset a different transmit channel of the first multi-channel transmitter,
wherein the first multi-channel transmitter is configured to select the local clock signal from any one of a plurality of available clock signals.
11. The invention of claim 1 , wherein the integrated circuit is a field-programmable gate array.
12. The invention of claim 10 , wherein the second sync stage comprises a different sync sub-stage for each different transmit channel, each different sync sub-stage comprises:
a multiplexer configured to select one of the available clock signals as the local clock signal; and
a sync cell configured to receive a corresponding copy of the first-synchronized reset signal and the local clock signal and generate one of the second-synchronized reset signals.
13. An integrated circuit comprising:
a first multi-channel transmitter having synchronization (sync) circuitry comprising:
a first sync stage configured to synchronize a reset signal to a local clock signal to generate a first-synchronized reset signal;
a second sync stage configured to synchronize each of a plurality of copies of the first-synchronized reset signal to the local clock signal to generate a plurality of second-synchronized reset signals, where each second-synchronized reset signal is applied to reset a different transmit channel of the first multi-channel transmitter, wherein
the first sync stage comprises a first-stage sync cell configured to receive the reset signal and the local clock signal and generate the first-synchronized reset signal,
the second sync stage comprises a different second-stage sync cell for each different transmit channel, each different sync cell configured to receive a corresponding copy of the first-synchronized reset signal and the local clock signal and generate one of the second-synchronized reset signals, and
wherein the first-stage sync cell comprises:
a first set of one or more buffers connected in series to receive the reset signal and generate a buffered reset signal;
a second set of one or more buffers connected in series to receive the local clock signal and generate a buffered local clock signal;
a first flip-flop connected to receive the buffered reset signal and the buffered local clock signal and generate a latched reset signal; and
a second flip-flop connected to receive the latched reset signal and the buffered local clock signal and generate the first-synchronized reset signal.
14. The integrated circuit of claim 13 , wherein comprising:
each second-stage sync cell comprises:
a first set of one or more buffers connected in series to receive the corresponding copy of the first-synchronized reset signal and generate a buffered first-synchronized reset signal;
a second set of one or more buffers connected in series to receive the local clock signal and generate a buffered local clock signal;
a first flip-flop connected to receive the buffered first-synchronized reset signal and the buffered local clock signal and generate a latched first-synchronized reset signal; and
a second flip-flop connected to receive the latched first-synchronized reset signal and the buffered local clock signal and generate the corresponding one of the second-synchronized reset signals.
15. An integrated circuit comprising:
a first multi-channel transmitter having synchronization (sync) circuitry comprising:
a first sync stage configured to synchronize a reset signal to a local clock signal to generate a first-synchronized reset signal;
a second sync stage configured to synchronize each of a plurality of copies of the first-synchronized reset signal to the local clock signal to generate a plurality of second-synchronized reset signals, where each second-synchronized reset signal is applied to reset a different transmit channel of the first multi-channel transmitter, wherein:
the first multi-channel transmitter is configured to generate a first set of transmit signals and the integrated circuit further comprises a second multi-channel transmitter configured to generate a second set of transmit signals, the first and second multi-channel transmitters can be configured to use a common clock signal to generate the first and second sets of transmit signals, and
each multi-channel transmitter is configured to select any one of a plurality of available clock signals as its local clock signal, wherein one of the available clock signals is a neighbor clock signal corresponding to the clock signal selected by the other multi-channel transmitter as its local clock signal.