Highly secure and extensive scan testing of integrated circuits
View Patent ↗In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.
1. A method for restricting access to scan testing of a logic device having a programmable fabric, the method comprising the logic device:
(a) receiving a set of instructions for programming the programmable fabric;
(b) programming the programmable fabric based on the set of instructions;
(c) deriving a multi-bit fabric pattern value from the programmed fabric;
(d) processing the multi-bit fabric pattern value to determine whether or not to restrict access to the scan testing of the logic device; and
(e) restricting access to the scan testing of the logic device if the processing of the multi-bit fabric pattern value fails to produce a specified fabric pattern result.
2. The invention of claim 1 , wherein the logic device is a field programmable gate array.
3. The invention of claim 1 , wherein the set of instructions is provided by external test equipment to the logic device via a JTAG interface of the logic device.
4. The invention of claim 1 , further comprising the logic device:
(f) receiving a multi-bit manufacturing key value;
(g) processing the multi-bit manufacturing key value to determine whether or not to restrict access to the scan testing of the logic device; and
(h) restricting access to the scan testing of the logic device if the processing of the multi-bit manufacturing key value fails to produce a specified manufacturing key result.
5. The invention of claim 4 , wherein the set of instructions and the multi-bit manufacturing key value are provided by external test equipment to the logic device via a JTAG interface of the logic device.
6. The invention of claim 4 , further comprising the logic device:
(i) receiving an instruction;
(j) processing the instruction;
(k) restricting access to the scan testing of the logic device if the instruction is not a special scan test instruction; and
(l) providing access to the scan testing of the logic device if (i) the instruction is the special scan test instruction AND (ii) the processing of the multi-bit fabric pattern value produces the specified fabric pattern result AND (iii) the processing of the multi-bit manufacturing key value produces the specified manufacturing key result.
7. The invention of claim 1 , further comprising the logic device:
(f) receiving an instruction;
(g) processing the instruction; and
(h) restricting access to the scan testing of the logic device if the instruction is not a special scan test instruction.
8. The invention of claim 7 , wherein the set of instructions and the special scan test instruction are provided by external test equipment to the logic device via a JTAG interface of the logic device.
9. A logic device comprising:
a programmable fabric; and
an input/output (I/O) interface, wherein the I/O interface is configured to:
(a) receive a set of instructions for programming the programmable fabric;
(b) program the programmable fabric based on the set of instructions;
(c) receive a multi-bit fabric pattern value from the programmed fabric;
(d) process the multi-bit fabric pattern value to determine whether or not to restrict access to the scan testing of the logic device; and
(e) restrict access to the scan testing of the logic device when the processing of the multi-bit fabric pattern value fails to produce a specified fabric pattern result.
10. The invention of claim 9 , wherein the logic device is a field programmable gate array.
11. The invention of claim 9 , wherein the I/O interface is a JTAG interface.
12. The invention of claim 9 , wherein the I/O interface is further configured to:
(f) receive a multi-bit manufacturing key value;
(g) process the multi-bit manufacturing key value to determine whether or not to restrict access to the scan testing of the logic device; and
(h) restrict access to the scan testing of the logic device if the processing of the multi-bit manufacturing key value fails to produce a specified manufacturing key result.
13. The invention of claim 12 , wherein the I/O interface is further configured to:
(i) receive an instruction;
(j) process the instruction;
(k) restrict access to the scan testing of the logic device if the instruction is not a special scan test instruction; and
(l) provide access to the scan testing of the logic device if (i) the instruction is the special scan test instruction AND (ii) the processing of the multi-bit fabric pattern value produces the specified fabric pattern result AND (iii) the processing of the multi-bit manufacturing key value produces the specified manufacturing key result.
14. The invention of claim 9 , wherein the I/O interface is further configured to:
(f) receive an instruction;
(g) process the instruction; and
(h) restrict access to the scan testing of the logic device if the instruction is not a special scan test instruction.
15. The invention of claim 9 , wherein the I/O interface comprises
a multi-bit state register;
a multi-bit scan register;
a multi-bit multiplexer connected to receive (i) data from the state register at a first mux input and (ii) data from the scan register at a second mux input and selectively output one of the data based on a scan-test mode signal; and
logic connected to receive the data output from the multiplexer, wherein:
when the scan-test mode signal is de-asserted, (i) the multiplexer selects the data from the state register to provide to the logic and (ii) the logic is configured to process the data from the state register to determine whether or not to set a scan-test-mode signal to indicate that the scan-test mode is enabled; and
when the scan-test mode signal is asserted, (i) the multiplexer selects the data from the scan register to provide to the logic and (ii) the logic is configured to process the data from the scan register during scan testing of the logic.
16. The invention of claim 15 , wherein the I/O interface further comprises a feedback path from the logic to the scan register to store data in the scan register that (i) is representative of results of the logic processing the data from the scan register and (ii) is shifted out of the scan register to external test equipment.
17. The invention of claim 16 , wherein the feedback path comprises a compactor that compresses the processing results of the logic for storage in the scan register.
18. A logic device having an input/output (I/O) interface comprising:
a multi-bit state register;
a multi-bit scan register;
a multi-bit multiplexer connected to receive (i) data from the state register at a first mux input and (i) data from the scan register at a second mux input and selectively output one of the data based on a scan-test mode signal; and
logic connected to receive the data output from the multiplexer, wherein:
when the scan-test mode signal de-asserted, (i) the multiplexer selects the data from the state register to provide to the logic and (ii) the logic is configured to process the data from the state register to determine whether or not to set a scan-test-mode signal to indicate that the scan-test mode is enabled; and
when the scan-test mode signal is asserted, (i) the multiplexer selects the data from the scan register to provide to the logic and (ii) the logic is configured to process the data from the scan register during scan testing of the logic.
19. The invention of claim 18 , wherein the I/O interface further comprises a feedback path from the logic to the scan register to store data in the scan register that (i) is representative of results of the logic processing the data from the scan register and (ii) is shifted out of the scan register to external test equipment.
20. The invention of claim 19 , wherein the feedback path comprises a compactor that compresses the processing results of the logic for storage in the scan register.