IP Library Granted Patent US 9,772,856
Granted Patent B2
US 9,772,856 · App. 14/327,811 · Granted Sep 26, 2017

System-level dual-boot capability in systems having one or more devices without native dual-boot capability

Inventors: Srirama Chandra (Beaverton, OR); Cleo Mui (Portland, OR); Cheng Jen Gwo (Portland, OR); Saurabh Chheda (Fremont, CA)
Assignee: Lattice Semiconductor Corporation
G06F9/4401G06F11/00G06F11/1417G06F12/0246G06F12/0638G06F2212/205G06F2212/7208
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Quick Facts
Patent No.
US 9,772,856
App. No.
14/327,811
Granted
Sep 26, 2017
Kind
B2
Abstract

In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.

Claims (54)

1. A system comprising:

a master programmable device (PD) having native dual-boot capability; and

a slave PD without native dual-boot capability and connected to the master PD, wherein:

the master PD has master volatile configuration memory;

the slave PD has slave volatile configuration memory;

a first non-volatile configuration memory in the system stores a master primary image for the master PD;

a second non-volatile configuration memory in the system stores a slave primary image for the slave PD; and

a third non-volatile memory in the system stores a master golden image for the master PD and a slave golden image for the slave PD, wherein the master golden image comprises a dual-boot function and one or more other master-PD functions and the system is designed such that:

during system power-up, (i) the master PD copies the master primary image from the first non-volatile memory into the master volatile memory and (ii) the slave PD copies the slave primary image from the second non-volatile memory into the slave volatile memory; and

in response to the master PD detecting that the master primary non-volatile image is invalid:

(1) the master PD copies the master golden image from the third non-volatile memory, instead of the master primary image from the first non-volatile configuration memory, into the master volatile memory of the master PD;

(2) then the master PD launches the dual-boot function of the master golden image;

(3) then the dual-boot function inhibits the one or more other master-PD functions of the master golden image;

(4) then the dual-boot function copies the slave golden image from the third non-volatile memory into the slave volatile memory of the slave PD; and

(5) then the dual-boot function enables the one or more other master-PD functions of the master golden image.

2. The system of claim 1 , wherein:

the master primary image is stored in master non-volatile memory within the master PD such that the first non-volatile memory is part of the master non-volatile memory within the master PD; and

the slave primary image is stored in slave non-volatile memory within the slave PD such that the second non-volatile memory is part of the slave non-volatile memory within the slave PD.

3. The system of claim 1 , wherein the first non-volatile memory is external to the master PD.

4. The system of claim 1 , wherein the second non-volatile memory is external to the slave PD.

5. The system of claim 1 , further comprising an external memory device, wherein the master golden image and the slave golden image are stored in the external memory device such that the third non-volatile memory is part of the external memory device.

6. The system of claim 5 , wherein the external memory device is directly connected to the master PD, but not directly connected to the slave PD.

7. The system of claim 5 , wherein:

the master and slave golden images are stored as a single, combined golden image in the external memory device; and

the dual-boot function of the master golden image is configured to extract and separately copy the master golden image and the slave golden image from the external memory device into the corresponding volatile memories of the master and slave PDs.

8. The system of claim 1 , wherein the system is programmed by:

(a) erasing memory for the master PD;

(b) then erasing, programming, and verifying memory for the slave PD; and

(c) then programming and verifying the memory for the master PD.

9. The system of claim 8 , wherein the system is designed such that, when power cycling occurs during any of steps (a), (b), and (c) of claim 8 , then steps (1)-(5) of claim 1 are implemented.

10. The system of claim 8 , further comprising one or more other slave PDs, wherein:

step (4) of claim 1 further comprises, for each other slave PD, the dual-boot function copying a corresponding slave golden image from the third non-volatile memory into corresponding slave volatile memory within the other slave PD; and

step (b) of claim 8 further comprises, for each other slave PD, erasing, programming, and verifying corresponding slave primary memory within the other slave PD.

11. A method comprising:

providing a master programmable device (PD) having volatile configuration memory and non-volatile configuration memory for storing a master primary image for the master PD, at least one slave PD without native dual-boot capability having volatile configuration memory and non-volatile configuration memory for storing a slave primary image for the slave PD, and a non-volatile memory device storing a master golden image for the master PD and a slave golden image for the slave PD; and

upon detecting that the master primary image for the master PD is invalid:

causing the master PD to copy the master golden image from the non-volatile memory device, instead of the master primary image from the non-volatile configuration memory, into the volatile configuration memory of the master PD; and

causing the master PD to copy the slave golden image from the non-volatile memory device into the volatile configuration memory of the slave PD.

12. The method of claim 11 , wherein the method further includes:

providing at least a second slave PD having volatile configuration memory and non-volatile configuration memory for storing a slave primary image for the second slave PD, and the memory device for storing a slave golden image for the second slave PD; and

upon detecting that the master primary image for the master PD is invalid:

causing the master PD to copy the slave golden image for the second slave PD from the memory device into the volatile configuration memory of the second slave PD.

13. A system comprising:

a master programmable device (PD) having volatile configuration memory and non-volatile configuration memory for storing a master primary image for the master PD,

at least one slave PD without native dual-boot capability having volatile configuration memory and non-volatile configuration memory for storing a slave primary image for the slave PD; and

a non-volatile memory device storing a master golden image for the master PD and a slave golden image for the slave PD;

wherein the master PD is configured, upon detecting that the master primary image for the master PD is invalid, to copy the master golden image from the non-volatile memory device, instead of the master primary image from the non-volatile configuration memory, into the volatile configuration memory of the master PD and to copy the slave golden image from the non-volatile memory device into the volatile configuration memory of the slave PD.

14. The system of claim 13 , wherein the memory device is external to the master PD and the slave PD.

15. The system of claim 14 , wherein the memory device is directly connected to the master PD, but not directly connected to the slave PD.

16. The system of claim 13 , wherein the master and slave golden images are stored as a combined golden image in the memory device.

17. The system of claim 13 including:

at least a second slave PD having volatile configuration memory and non-volatile configuration memory for storing a slave primary image for the second slave PD; and

the memory device storing a slave golden image for the second slave PD;

wherein the master PD is configured, upon detecting that the master primary image for the master PD is invalid to copy the slave golden image for the second slave PD from the memory device into the volatile configuration memory of the second slave PD.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
SECURITY INTEREST Recorded Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035309/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2014
From: CHHEDA, SAURABH
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 033308/0367 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2014
From: CHANDRA, SRIRAMA; MUI, CLEO; GWO, CHENG JEN
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 033286/0061 →
Continuity (1)
Related Publication 20160011878A1 · Jan 14, 2016