Comparator with jitter mitigation
View Patent ↗In one embodiment, a circuit such as a comparator circuit includes a differential stage adapted to receive a differential input signal and first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal. The circuit may include an output stage coupled to the first and second diodes at the first and second differential output nodes, with the output stage adapted to convert the differential output signal to a single ended output signal. The circuit may also include a current source adapted to selectively provide a reference current to the first or second diode in an off state to reduce voltage swing of the first or second diode between the off and an on state.
1. A circuit comprising:
a differential stage adapted to receive a differential input signal;
first and second diodes coupled to the differential stage, wherein the first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal; and
a current source adapted to selectively provide a reference current to the first or second diode in an off state to reduce voltage swing of the first or second diode between the off and an on state.
2. The circuit of claim 1 including an output stage coupled to the first and second diodes at the first and second differential output nodes, wherein the output stage is adapted to convert the differential output signal to a single ended output signal.
3. The circuit of claim 1 , wherein the current source is a first current source and the reference current is a first reference current, the circuit including a second current source adapted to selectively provide a second reference current to the first or second differential output node to selectively switch the first or second diode in response to the differential input signal.
4. The circuit of claim 3 including:
third and fourth diodes coupled to the differential stage; and
a third current source adapted to selectively provide a third reference current to the third or the fourth diode in response to the differential input signal,
wherein the third and fourth diodes are adapted to selectively switch on and off in response to the third reference current.
5. A circuit comprising:
a differential stage adapted to receive a differential input signal;
first and second diodes coupled to the differential stage, wherein the first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal; and
a disable circuit adapted to selectively turn off the differential stage in response to a disable signal to reduce power consumption of the comparator circuit.
6. The circuit of claim 1 , wherein the circuit is part of a programmable logic device (PLD).
7. A method of operating a circuit, the method comprising:
receiving a differential input signal at a differential stage;
selectively switching on and off first and second diodes coupled to the differential stage to provide a differential output signal at first and second differential output nodes in response to the differential input signal; and
selectively providing a reference current to the first or second diode in an off state to reduce a voltage swing of the first or second diode between the off state and an on state.
8. The method of claim 7 including converting the differential output signal to a single ended output signal using an output stage.
9. The method of claim 7 , wherein the reference current is a first reference current, the method including selectively providing a second reference current to the first or second differential output node to selectively switch the first or second diode in response to the differential input signal.
10. The method of claim 9 including selectively providing a third reference current to a third or a fourth diode coupled to the differential stage in response to the differential input signal.
11. The method of claim 10 including selectively switching on and off the third and fourth diodes in response to the third reference current.
12. A method of operating a circuit, the method comprising:
receiving a differential input signal at a differential stage;
selectively switching on and off first and second diodes coupled to the differential stage to provide a differential output signal at first and second differential output nodes in response to the differential input signal; and
disabling the differential stage in response to a disable signal to reduce power consumption of the circuit.
13. A programmable logic device (PLD) comprising:
a differential stage adapted to receive a differential input signal;
first and second diodes coupled to the differential stage, wherein the first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal;
an output stage coupled to the first and second diodes at the first and second differential output nodes, wherein the output stage is adapted to convert the differential output signal to a single ended output signal; and
a current source adapted to selectively provide a reference current to the first or second diode in an off state to reduce a voltage swing of the first or second diode between the off state and an on state.