Dual-port SRAM with bit line clamping
View Patent ↗In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.
1. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a first stage clamping circuit operable to clamp the internal node to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the internal node during the write operation;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a second stage clamping circuit operable to clamp the plurality of bit lines to a clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line during the write operation.
2. The memory of claim 1 , wherein the memory comprises a dual-port memory.
3. The memory of claim 1 , wherein the second stage clamping circuit includes a plurality of clamping transistors corresponding to the plurality of bit lines.
4. The memory of claim 1 , wherein the memory comprises SRAM.
5. The memory of claim 1 , wherein the memory is embedded in a programmable logic device.
6. The memory of claim 5 , wherein the programmable logic device is a field programmable gate array.
7. The memory of claim 1 , wherein each bit line is one of a complementary bit line pair.
8. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a clamping circuit operable to clamp the plurality of bit lines to a clamping voltage, wherein the clamping circuit is further operable to unclamp the selected bit line driven by the write driver during the write operation.
9. The memory of claim 8 , wherein the memory comprises a dual-port memory.
10. The memory of claim 8 , wherein the clamping circuit includes a plurality of clamping transistors corresponding to the plurality of bit lines.
11. The memory of claim 8 , wherein each bit line is one of a complementary bit line pair.
12. A memory, comprising:
a plurality of bit lines;
a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
a multiplexer for selectively coupling the driven bit line to the internal node; and
a clamping circuit operable to clamp the internal node to a clamping voltage, wherein the clamping circuit is further operable to unclamp the internal node during the write operation.