ESD protection using shared RC trigger
View Patent ↗In one embodiment, an integrated circuit includes multiple I/O banks, each bank having multiple I/O-ESD tiles, each tile having one or more I/O circuits and electrostatic discharge (ESD) protection circuitry for the one or more I/O circuits in the tile. The ESD circuitry for one tile includes at least one RC-triggered clamp, whose resistance is provided by a resistor shared by one or more other RC-triggered clamps in one or more other tiles of the same bank and whose capacitance is provided by a combination of distributed capacitors, one for each of those two or more RC-triggered clamps. Each tile may have multiple instances of such RC-triggered clamps providing ESD protection for different (e.g., power supply and/or bus) nodes. The shared resistors are variable to allow different instances of the same ESD circuitry design to be implemented with the same time constant for different banks having different numbers of tiles.
1. An integrated circuit comprising at least a first input/output (I/O) bank comprising at least two tiles, each of the at least two tiles comprising:
one or more I/O circuits; and
electrostatic discharge (ESD) circuitry configured to provide ESD protection for the one or more I/O circuits in the tile, wherein:
the ESD circuitry of each of the at least two tiles comprises a first resistance-capacitance (RC)-triggered clamp;
the first I/O bank comprises a shared first resistor and a plurality of distributed first capacitors, wherein:
the shared first resistor is shared by the first RC-triggered clamps in the at least two tiles; and
the first RC-triggered clamp in each of the at least two tiles has its own distributed first capacitor connected in parallel with the rest of the distributed first capacitors for the rest of the first RC-triggered clamps in the at least two tiles.
2. The integrated circuit of claim 1 , wherein:
the ESD circuitry in each of the at least two tiles of the first I/O bank further comprises a second RC-triggered clamp;
the first I/O bank further comprises a shared second resistor and a plurality of distributed second capacitors, wherein:
the shared second resistor is shared by the second RC-triggered clamps of the at least two tiles; and
the second RC-triggered clamp in each of the at least two tiles has its own distributed second capacitor connected in parallel with the rest of the distributed second capacitors for the rest of the second RC-triggered clamps of the at least two tiles.
3. The integrated circuit of claim 1 , wherein the ESD circuitry in each of the at least two tiles of the first I/O bank comprises a different RC-triggered clamp for each of a plurality of power supply nodes of the integrated circuit.
4. The integrated circuit of claim 3 , wherein the ESD circuitry in each of the at least two tiles of the first I/O bank further comprises an RC-triggered clamp for a bus associated with hot socket capability of the first I/O bank.
5. The integrated circuit of claim 1 , wherein the shared first resistor is a variable resistor that can be selectively configured to provide any of a plurality of different resistance levels such that different instances of the ESD circuitry can be configured in different I/O banks of the integrated circuit having different numbers of tiles.
6. The integrated circuit of claim 5 , wherein the different instances of the ESD circuitry in the different tiles of the different I/O banks have equal time constants.
7. The integrated circuit of claim 1 , wherein:
the first RC-triggered clamp is configured to provide ESD protection for a first power supply node of the integrated circuit; and
the ESD circuitry further comprises:
a second RC-triggered clamp configured to provide ESD protection for a second power supply node of the integrated circuit; and
a third RC-triggered clamp configured to provide ESD protection for a third power supply node of the integrated circuit.
8. The integrated circuit of claim 7 , wherein:
the first, second, and third power supply nodes have three different maximum voltage levels; and
the first, second, and third RC clamps have three differently sized shunt transistors corresponding to the three different maximum voltage levels.
9. The integrated circuit of claim 7 , wherein the ESD circuitry further comprises a fourth RC-triggered clamp configured to provide ESD protection for a bus associated with hot socket capability of the first I/O bank.
10. The integrated circuit of claim 1 , wherein the ESD circuitry further comprises one or more diodes configured to provide ESD protection for negative ESD events.
11. The integrated circuit of claim 1 , wherein:
the ESD circuitry in each of the at least two tiles of the first I/O bank further comprises a second RC-triggered clamp;
the first I/O bank further comprises a shared second resistor and a plurality of distributed second capacitors, wherein:
the shared second resistor is shared by all of the second RC-triggered clamps in the first I/O bank; and
the second RC-triggered clamp in each of the at least two tiles has its own distributed second capacitor connected in parallel with the rest of the distributed second capacitors for the rest of the second RC-triggered clamps in the first I/O bank;
the ESD circuitry in each of the at least two tiles of the first I/O bank comprises a different RC-triggered clamp for each of a plurality of power supply nodes of the integrated circuit;
the ESD circuitry in each of the at least two tiles of the first I/O bank further comprises an RC-triggered clamp for a bus associated with hot socket capability of the first I/O bank;
the shared first resistor is a variable resistor that can be selectively configured to provide any of a plurality of different resistance levels such that different instances of the ESD circuitry can be configured in different I/O banks of the integrated circuit having different numbers of tiles;
the different instances of the ESD circuitry in the different tiles of the different I/O banks have equal time constants; and
the ESD circuitry further comprises one or more diodes configured to provide ESD protection for negative ESD events.