Mixed-width memory techniques for programmable logic devices

1. A computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD); and

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting a mixed-mode memory operation in the design, the mixed-mode memory operation specifying memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width, each of the plurality of embedded memory blocks being associated with a corresponding write enable signal to be used for enabling each embedded memory block for writing,

determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and

modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks, the modifying comprising generating a write mask signal for each of the reduced number of embedded memory block, using the write enable signals, to allow a plurality of data portions to be written without overwriting each other in the reduced number of embedded memory blocks.

2. The computer-implemented method of claim 1 , wherein:

the reduced number of embedded memory blocks is a minimum number of embedded memory blocks to implement the mixed-mode memory operation; and

the minimum number of embedded memory blocks is determined based on a size of the mixed-mode memory operation relative to the size of each embedded memory block.

3. The computer-implemented method of claim 1 , wherein the detecting comprises checking whether the specified memory access writes data to only a portion of each embedded memory block and leaves an unused portion of each embedded memory block.

4. The computer-implemented method of claim 3 , wherein the checking comprises comparing the read data width of the mixed-mode memory operation or the write data width of the mixed-mode memory operation with the fixed data width of each embedded memory block.

5. The computer-implemented method of claim 3 , wherein:

each of the plurality of embedded memory blocks is associated with a corresponding write data signal to be used for passing data to be written in the each embedded memory block; and

the modifying comprises reassigning the write data signals to the reduced number of embedded memory blocks such that data to be written is spread among the reduced number of embedded memory blocks with at least one of the unused portions eliminated.

6. The computer-implemented method of claim 1 , wherein the modifying comprises combining or reassigning the write enable signals to the reduced number of embedded memory blocks.

7. The computer-implemented method of claim 1 , wherein:

the user design describes the mixed-mode memory operation as a user-defined write port and a user-defined read port that assign data and control signals to the plurality of embedded memory blocks to cascade the plurality of embedded memory blocks; and

the user-defined read and write ports define the read and write data widths.

8. The computer-implemented method of claim 1 , further comprising:

generating configuration data to configure physical components of the PLD in accordance with the synthesized design; and

programming the PLD with the configuration data.

9. The computer-implemented method of claim 1 , wherein the modifying comprises determining new positions within the reduced number of embedded memory blocks for the remapped memory access, the new positions including positions for a remapped memory block that are spread over two of the embedded memory blocks.

10. The computer-implemented method of claim 1 , wherein:

each of the plurality of embedded memory blocks is associated with a corresponding read data signal to be used for passing data to be read from the each embedded memory block;

each of the plurality of embedded memory blocks is associated with a corresponding read enable signal to be used for enabling each embedded memory block for reading; and

the modifying comprises combining the read data signals and the read enable signals to read data with different read and write data widths.

11. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD), and

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting a mixed-mode memory operation in the design, the mixed-mode memory operation specifying memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width, each of the plurality of embedded memory blocks being associated with a corresponding write enable signal to be used for enabling each embedded memory block for writing,

determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and

modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks, the modifying comprising generating write mask signal for each of the reduced number of embedded memory block, using the write enable signals, to allow a plurality of data portions to be written without overwriting each other in the reduced number of embedded memory blocks.

12. The system of claim 11 , wherein:

the reduced number of embedded memory blocks is a minimum number of embedded memory blocks to implement the mixed-mode memory operation; and

the minimum number of embedded memory blocks is determined based on a size of the mixed-mode memory operation relative to the size of each embedded memory block.

13. The system of claim 11 , wherein the detecting comprises checking whether the specified memory access writes data to only a portion of each embedded memory block and leaves an unused portion of each embedded memory block.

14. The system of claim 13 , wherein the checking comprises comparing the read data width of the mixed-mode memory operation or the write data width of the mixed-mode memory operation with the fixed data width of each embedded memory block.

15. The system of claim 13 , wherein:

each of the plurality of embedded memory blocks is associated with a corresponding write data signal to be used for passing data to be written in the each embedded memory block; and

the modifying comprises reassigning the write data signals to the reduced number of embedded memory blocks such that data to be written is spread among the reduced number of embedded memory blocks with at least one of the unused portions eliminated.

16. The system of claim 11 , wherein the modifying comprises combining or reassigning the write enable signals to the reduced number of embedded memory blocks.

17. The system of claim 11 , wherein the computer-implemented method further comprises:

generating configuration data to configure physical components of the PLD in accordance with the synthesized design; and

programming the PLD with the configuration data.

18. The system of claim 11 , wherein the modifying comprises determining new positions within the reduced number of embedded memory blocks for the remapped memory access, the new positions including positions for a remapped memory block that are spread over two of the embedded memory blocks.

19. The system of claim 11 , wherein:

each of the plurality of embedded memory blocks is associated with a corresponding read data signal to be used for passing data to be read from the each embedded memory block;

each of the plurality of embedded memory blocks is associated with a corresponding read enable signal to be used for enabling each embedded memory block for reading; and

the modifying comprises combining the read data signals and the read enable signals to read data with different read and write data widths.

20. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD); and

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting a mixed-mode memory operation in the design, the mixed-mode memory operation specifying memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width, each of the plurality of embedded memory blocks being associated with a corresponding write enable signal to be used for enabling each embedded memory block for writing,

determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and

modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks, the modifying comprising generating a write mask signal for each of the reduced number of embedded memory block, using the write enable signals, to allow a plurality of data portions to be written without overwriting each other in the reduced number of embedded memory blocks.