CLOCK ASSIGNMENTS FOR PROGRAMMABLE LOGIC DEVICE
Various techniques are provided to perform clock assignments in a programmable logic device (PLD). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD), synthesizing the design into a plurality of components of the PLD configured to perform the operations, and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD. Additional methods, systems, machine-readable mediums, and other techniques are also provided.
1 . A computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD);
synthesizing the design into a plurality of components of the PLD configured to perform the operations; and
performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD.
2 . The computer-implemented method of claim 1 , wherein the simulated annealing process comprises:
generating a new layout of the components by changing positions of at least a subset of the components;
calculating changes in the system cost including changes to the clock assignment cost resulting from the changed positions; and
selectively accepting the new layout based on the changes in the system cost including the changes to the clock assignment cost and a temperature of the simulated annealing process.
3 . The computer-implemented method of claim 2 , further comprising repeating the generating, the calculating, and the accepting in accordance with a cooling schedule of the simulated annealing process.
4 . The computer-implemented method of claim 1 , further comprising selectively performing a clock violation mitigation process during the simulated annealing process.
5 . The computer-implemented method of claim 4 , wherein the clock violation mitigation process comprises:
selecting one of the global clock signals associated with a clock assignment violation in a first region of the PLD;
generating a new layout by changing positions of the components associated with the selected global clock signal from the first region of the PLD to a second region of the PLD.
6 . The computer-implemented method of claim 5 , wherein the selecting one of the global clock signals comprises selecting one of the global clock signals associated with less than a maximum number of associated components.
7 . The computer-implemented method of claim 6 , further comprising:
increasing the maximum number; and
repeating the clock violation mitigation process using the increased maximum number.
8 . The computer-implemented method of claim 4 , wherein the performance of the clock violation mitigation process is conditioned on a minimum number of new layouts being accepted by the simulated annealing process.
9 . The computer-implemented method of claim 1 , wherein the clock assignment cost is calculated based on a number of clock assignment violations in each of a plurality of regions of the PLD, wherein each region has a finite number of assignable clock resources.
10 . The computer-implemented method of claim 1 , wherein the system cost is calculated based on one or more of a wire length, a timing analysis, and a congestion analysis.
11 . A system comprising:
a processor; and
a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD),
synthesizing the design into a plurality of components of the PLD configured to perform the operations, and
performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD.
12 . The system of claim 11 , wherein the simulated annealing process comprises:
generating a new layout of the components by changing positions of at least a subset of the components;
calculating changes in the system cost including changes to the clock assignment cost resulting from the changed positions; and
selectively accepting the new layout based on the changes in the system cost including the changes to the clock assignment cost and a temperature of the simulated annealing process.
13 . The system of claim 12 , wherein the simulated annealing process further comprises repeating the generating, the calculating, and the accepting in accordance with a cooling schedule.
14 . The system of claim 11 , wherein the computer-implemented method further comprises selectively performing a clock violation mitigation process during the simulated annealing process.
15 . The system of claim 14 , wherein the clock violation mitigation process comprises:
selecting one of the global clock signals associated with a clock assignment violation in a first region of the PLD; and
generating a new layout by changing positions of the components associated with the selected global clock signal from the first region of the PLD to a second region of the PLD.
16 . The system of claim 15 , wherein the selecting one of the global clock signals comprises selecting a clock signal associated with less than a maximum number of associated components.
17 . The system of claim 16 , wherein the clock violation mitigation process further comprises:
increasing the maximum number; and
repeating the clock violation mitigation process using the increased maximum number.
18 . The system of claim 14 , wherein the performance of the clock violation mitigation process is conditioned on a minimum number of new layouts being accepted by the simulated annealing process.
19 . The system of claim 11 , wherein the clock assignment cost is calculated based on a number of clock assignment violations in each of a plurality of regions of the PLD, wherein each region has a finite number of assignable clock resources.
20 . A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD);
synthesizing the design into a plurality of components of the PLD configured to perform the operations; and
performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD.