Incrementer absorption into multiplier logic for programmable logic devices

1. A computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD); and

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting an incrementer-multiplier operation in the design, and

merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components, wherein the merged incrementer-multiplier operation comprises at least two addition operations configured to operate substantially in parallel.

2. The computer-implemented method of claim 1 , wherein the synthesizing comprises:

decomposing the multiplier portion of the incrementer-multiplier operation into one or more of the addition operations; and

the merging comprises merging the incrementer portion with the decomposed multiplier portion, wherein the merged portions are configured to use common glue logic.

3. The computer-implemented method of claim 2 , wherein:

each addition operation comprises a carry-in input; and

the common glue logic is configured to provide an element of a multiplier operand of the incrementer-multiplier operation to one of the carry-in inputs.

4. The computer-implemented method of claim 2 , wherein:

each addition operation comprises an operand input;

the common glue logic is configured to provide a partial product to the operand input; and

at least one of the addition operations is configured to shift the partial product with unit paddings.

5. The computer-implemented method of claim 2 , wherein:

each addition operation comprises an operand input; and

the common glue logic is configured to provide a shifted partial product with unit paddings to the operand input.

6. The computer-implemented method of claim 1 , wherein the incrementer-multiplier operation comprises a first incrementer-multiplier operation, and wherein the synthesizing comprises:

determining the first incrementer-multiplier operation has a multiplier operand bit-width that is a power of two;

detecting a second incrementer-multiplier operation in the design; and

merging an incrementer portion of the second incrementer-multiplier operation with a multiplier portion of the second incrementer-multiplier operation to reduce the plurality of PLD components.

7. The computer-implemented method of claim 1 , wherein:

the addition operations are implemented by at least one look up table (LUT); and

the at least one LUT is implemented within a programmable logic block of the PLD.

8. The computer-implemented method of claim 7 , wherein:

the programmable logic block comprises a plurality of logic cells; and

each one of the at least one LUT is associated with a corresponding one of the logic cells.

9. The computer-implemented method of claim 7 , wherein:

each one of the at least one LUT is a four-input LUT; and

the four-input LUT is configured to implement a one bit addition operation.

10. The computer-implemented method of claim 1 , further comprising:

generating configuration data to configure physical components of the PLD in accordance with the synthesized design; and

programming the PLD with the configuration data.

11. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD),

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting an incrementer-multiplier operation in the design, and

merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.

12. The system of claim 11 , wherein the synthesizing comprises:

decomposing the multiplier portion of the incrementer-multiplier operation into one or more addition operations; and

merging the incrementer portion with the decomposed multiplier portion, wherein the merged portions are configured to use common glue logic.

13. The system of claim 12 , wherein:

each addition operation comprises a carry-in input; and

the common glue logic is configured to provide an element of a multiplier operand of the incrementer-multiplier operation to one of the carry-in inputs.

14. The system of claim 12 , wherein:

each addition operation comprises an operand input;

the common glue logic is configured to provide a partial product to the operand input; and

at least one of the addition operations is configured to shift the partial product with unit paddings.

15. The system of claim 12 , wherein:

each addition operation comprises an operand input; and

the common glue logic is configured to provide a shifted partial product with unit paddings to the operand input.

16. The system of claim 11 , wherein the incrementer-multiplier operation comprises a first incrementer-multiplier operation, and wherein the synthesizing comprises:

determining the first incrementer-multiplier operation has a multiplier operand bit-width that is a power of two;

detecting a second incrementer-multiplier operation in the design; and

merging an incrementer portion of the second incrementer-multiplier operation with a multiplier portion of the second incrementer-multiplier operation to reduce the plurality of PLD components.

17. The system of claim 11 , wherein:

the merged incrementer-multiplier operation comprises at least two addition operations configured to operate substantially in parallel;

the addition operations are implemented by at least one look up table (LUT); and

the at least one LUT is implemented within a programmable logic block of the PLD.

18. The system of claim 17 , wherein:

the PLB comprises a plurality of logic cells;

each one of the at least one LUT is a four-input LUT associated with a corresponding one of the logic cells; and

the four-input LUT is configured to implement a one bit addition operation.

19. The system of claim 11 , wherein the computer-implemented method further comprises:

generating configuration data to configure physical components of the PLD in accordance with the synthesized design; and

programming the PLD with the configuration data.

20. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD);

synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:

detecting an incrementer-multiplier operation in the design, and

merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.