Collector current driver for a bipolar junction transistor temperature transducer

1. A circuit, comprising:

a current source configured to source a target current;

a differential amplifier configured to compare the target current to a duplicate difference current to generate a feedback voltage;

an output transistor responsive to the feedback voltage and configured to source an emitter current to a bipolar transistor;

a difference circuit configured to subtract a sum current equaling a sum of the emitter current and a base current for the bipolar transistor from a first current equaling twice the emitter current to produce a difference current; and

a difference current mirror configured to duplicate the difference current to provide the duplicate difference current.

2. The circuit of claim 1 , further comprising:

a first load; and

a second load, wherein the differential amplifier is configured to compare the target current to the duplicate difference current responsive to voltages developed at a terminal for each of the first and second loads.

3. The circuit of claim 2 , further comprising:

a first current path coupled to the first load;

a second current path coupled to the second load; and

a target current mirror configured to duplicate the target current into a duplicate target current driven through the second current path, wherein the current source is configured to drive the target current through the first current path.

4. The circuit of claim 1 , further comprising:

a duplicate output transistor matched to the output transistor, wherein the duplicate output transistor is configured to drive a summing current mirror with a duplicate of the emitter current responsive to the feedback voltage.

5. The circuit of claim 4 , wherein the summing current mirror is further configured to receive the base current to provide the sum current and to duplicate the sum current to provide a duplicate sum current, and wherein the difference circuit is further configured to subtract the sum current from the first current using the duplicate sum current.

6. The circuit of claim 1 , further comprising:

a duplicate output transistor configured to provide the first current responsive to the feedback voltage, wherein the duplicate output transistor is further configured to drive the first current to the difference circuit through a feedback current path.

7. The circuit of claim 6 , wherein the difference circuit comprises a first transistor coupled to the feedback current path and a second transistor coupled to the feedback current path, and wherein the first transistor is configured to sink the duplicate sum current into ground, and wherein the second transistor is configured to sink the difference current into ground.

8. The circuit of claim 6 , wherein the output transistor and the duplicate output transistor both comprise PMOS transistors.

9. The circuit of claim 6 , wherein the duplicate output transistor comprises a single transistor of twice a size for the output transistor.

10. The circuit of claim 6 , wherein the output transistor and the duplicate output transistor each has a source coupled to a power supply node.

11. A method, comprising:

driving a target current through a first load to generate a first voltage;

generating a feedback voltage responsive to a difference between the first voltage and a second voltage;

driving an emitter current into a bipolar transistor responsive to the feedback voltage;

providing a duplicate current equaling twice the emitter current responsive to the feedback voltage;

subtracting a sum of the emitter current and a base current for the bipolar transistor from the duplicate current to provide a difference current; and

driving a duplicate of the difference current through a second load to generate the second voltage such that the difference current equals the collector current.

12. The method of claim 11 , wherein driving the emitter current comprising driving a gate of an output transistor with the feedback voltage to drive the emitter current from the output transistor to an emitter terminal for the bipolar transistor.

13. The method of claim 11 , further comprising driving the target current into a first current mirror to generate the first voltage.

14. The method of claim 13 , wherein driving the target current into a first current mirror to generate the first voltage comprises:

driving the target current into an array of M first transistors arranged in parallel, M being an integer greater than one; and

for an array of M first current paths, selecting N of the first current paths to conduct responsive to a control signal such that a mirrored current flows in the subset of the first current paths proportional to a ratio N/M, wherein N is a positive integer less than M.

15. The method of claim 14 , wherein selecting N of the first current paths comprises turning on a switch in each of the selected first current paths responsive to the control signal.

16. A circuit comprising:

a current source for providing a target collector current for a bipolar transistor;

a first current mirror for providing a mirror current equal to the bipolar transistor's collector current (I C ); and

a differential amplifier for generating a feedback voltage responsive to a difference between the target collector current and the mirror current,

wherein the feedback voltage is adapted to vary the emitter current (I E ) provided to the bipolar transistor for maintaining the bipolar transistor's collector current equal to the target collector current.

17. The circuit of claim 16 including switches for varying the target collector current.

18. The circuit of claim 16 including a first output transistor for providing the emitter current to the bipolar transistor,

wherein the differential amplifier is coupled to the gate of the output transistor for applying the feedback voltage to the gate.

19. The circuit of claim 16 including a second current mirror for providing a sum current equal to the sum of the base and emitter currents (I B +I E ) of the bipolar transistor,

wherein:

the first current mirror is adapted to receive a duplicate current equal to twice the bipolar transistor's emitter current (2I E ); and

the second current mirror is adapted to subtract the sum current (I B +I E ) from the duplicate current (2I E ) to provide the bipolar transistor's collector current (I C ) as the current mirrored by the first current mirror.

20. The circuit of claim 19 including:

a first output transistor for providing the emitter current (I E ) to the bipolar transistor;

a second output transistor for providing a duplicate current equal to the bipolar transistor's emitter current (I E ) to the second current mirror; and

a third output transistor for providing the duplicate current equal to twice the bipolar transistor's emitter current (2I E ) to the first current mirror,

wherein the differential amplifier is coupled to the gates of the first, second, and third output transistors for applying the feedback voltage to the gates.