Testing of soft error detection logic for programmable logic devices
View Patent ↗In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.
1. A programmable logic device (PLD) comprising:
configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the cell and a second port for writing RAM data to the cell;
soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory cell by calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory; and
a fuse configurable in a first logic state to enable RAM data from the configuration memory cell to be read through the first port for calculating the present data value of the configuration memory and configurable in a second logic state to prevent RAM data from being read from the configuration memory cell.
2. The PLD of claim 1 including:
an address shift register adapted to provide wordline signals on a wordline to the configuration memory cell; and
a multiplexer coupled between the address shift register and the wordline, the multiplexer having a first input coupled to the address shift register, a second input coupled to a second signal source, an output coupled to the wordline, and a select input coupled to the fuse,
wherein the multiplexer couples the address shift register to the wordline with the fuse configured in the first logic state to enable reading from the configuration memory cell through the first port and couples the second signal source to the wordline with the fuse configured in the second logic state to disable reading from the configuration memory cell through the first port.
3. The PLD of claim 1 including a second fuse configurable in a first logic state to enable RAM data to be written to the configuration memory cell through the second port and configurable in a second logic state to prevent RAM data from being written to the configuration memory cell through the second port.
4. The PLD of claim 1 , wherein the SED logic is implemented within configuration logic of the programmable logic device.
5. The PLD of claim 1 , wherein the SED logic is adapted to calculate a present cyclic redundancy code (CRC) value for comparison with a pre-calculated CRC value.
6. The PLD of claim 1 , wherein the fuse is a configuration memory cell.
7. A programmable logic device (PLD) comprising:
configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the cell and a second port for writing RAM data to the cell;
soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory; and
a fuse configurable in a first logic state to enable RAM data from the configuration memory cell to be read through the first port for checking for an error in the data and configurable in a second logic state to prevent RAM data from being read from the configuration memory cell.
8. The PLD of claim 7 including:
an address shift register adapted to provide wordline signals on a wordline to the configuration memory cell; and
a multiplexer coupled between the address shift register and the wordline, the multiplexer having a first input coupled to the address shift register, a second input coupled to a second signal source, an output coupled to the wordline, and a select input coupled to the fuse,
wherein the multiplexer couples the address shift register to the wordline with the fuse configured in the first logic state to enable reading from the configuration memory cell through the first port and couples the second signal source to the wordline with the fuse configured in the second logic state to disable reading from the configuration memory cell through the first port.
9. The PLD of claim 7 including a second fuse configurable in a first logic state to enable RAM data to be written to the configuration memory cell through the second port and configurable in a second logic state to prevent RAM data from being written to the configuration memory cell through the second port.
10. The PLD of claim 7 , wherein the SED logic is implemented within configuration logic of the programmable logic device.
11. A method of testing soft error detection (SED) logic for correct operation within a programmable logic device (PLD), the PLD having configuration memory that includes a configuration memory cell, the method comprising:
writing data representing a soft error to the configuration memory cell; and
with the SED logic:
reading data stored in the configuration memory including the configuration memory cell;
calculating from the read data a present data value for the configuration memory; and
comparing the present data value with a pre-calculated data value for the configuration memory that does not include the soft error data written to the configuration memory cell,
wherein the SED logic is operating correctly if the present data value does not match the pre-calculated data value.
12. The method of claim 11 including, prior to the SED logic reading the data stored in the configuration memory cell, configuring the PLD from a second logic state to a first logic state to enable the SED logic to read from the configuration memory cell, wherein the SED logic is prevented from reading from the configuration memory cell in the second logic state.
13. The method of claim 12 , wherein configuring the PLD includes configuring a fuse within the PLD from the second logic state to the first logic state.
14. The method of claim 11 , wherein if the present data value does not match the pre-calculated data value, indicating a soft error has been detected.
15. The method of claim 11 , wherein:
the configuration memory cell has first and second ports;
the data representing a soft error is written to the configuration memory cell through the second port; and
the data representing the soft error is read from the configuration memory cell through the first port.
16. The method of claim 15 , wherein the configuration memory cell is adapted to function as random access memory (RAM), the first port adapted for writing configuration data to the cell and the second port adapted for writing RAM data to the cell.